Cisco

ASIC DFT STA Technical Lead

Cisco$168K — $241K *
Technical Services
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree with 8+ years of experience, Master's with 6+, or PhD with 3+ years in relevant field.
  • Experience in RTL design, CDC/RDC, and conformal verification.
  • Expertise in timing constraint development and verification.
  • Proficiency in scripting with Perl, TCL, Python, or Makefile.

Responsibilities

  • Develop timing constraints for block, sub-chip, and full-chip in test modes.
  • Perform quality checks on timing constraints and handle unconstrained endpoints.
  • Conduct SDC validation and CDC delay checks.
  • Create methodologies and guidelines to enhance STA processes and execution.
  • Resolve design and flow issues effectively.

Benefits

  • Engage in cutting-edge projects in networking chip technologies.
  • Collaborate with cross-functional teams to enhance your technical communication skills.
  • Gain exposure to physical design signoff activities and post-silicon validation.
Full Job Description
The application window is expected to close on: 08/25/2026
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Your Impact

You will be in the Silicon One development organization as an ASIC DFT STA Technical Lead. You are a detail-oriented STA engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Key Responsibilities
  • Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.
  • Check timing for unconstrained endpoints, no clock, etc.
  • Your role may include SDC validation, CDC delay check, and SDC flow development.
  • Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.


Minimum Qualifications
  • Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
  • Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development.
  • Prior working experience in timing constraint development and verification.
  • Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile.


Preferred Qualifications
  • Masters degree + 15+ years experience.
  • Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints.
  • Prior working experience with RTL design, CDC/RDC and conformal verification.
  • Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.
  • Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime.
  • Prior working experience with synthesis tools: Synopsys Fusion/design Compiler.
  • Prior working experience with Tessent tool like DFT insertion in RTL.

About Cisco

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79,500 employees
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Net Income
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Founded
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