Cisco

ASIC DFT Engineer

Cisco$165K — $241K *
Technical Services
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's or Master's Degree in Electrical or Computer Engineering; 7+ years of experience required.
  • Experience with innovative DFT, test, and silicon engineering trends.
  • Proficient in JTAG protocols, Scan, BIST architectures including memory BIST, and boundary scan.
  • Familiarity with ATPG and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime.
  • Experience in gate level simulation and debugging with VCS and other simulators.

Responsibilities

  • Implement DFT features that support ATE, in-system testing, and debugging needs.
  • Develop innovative DFT IP in collaboration with cross-functional teams for chip design integration.
  • Collaborate with design and physical design teams for test logic integration and validation.
  • Participate in creating innovative DFT and physical design aspects for new silicon device models.
  • Craft solutions and debug with minimal mentorship.

Benefits

  • Exposure to developing groundbreaking next-generation networking chips.
  • Involvement with full chip design integration and cross-functional collaboration.
  • Opportunities to work on innovative test strategies for new silicon technologies.
  • Potential for working in a fast-paced and cutting-edge environment.
  • Engagement in comprehensive post-silicon validation processes.
Full Job Description
The application window is expected to close on: 09/01/2026
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Your Impact:

You will be in the Silicon One development organization as an ASIC DFT Engineer . You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Key Responsibilities:

  • Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
  • Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
  • Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
  • Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
  • The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.


Minimum Qualifications:

  • Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
  • Prior experience working in the latest innovative trends in DFT, test and silicon engineering.
  • Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
  • Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
  • Prior experience working with Gate level simulation, debugging with VCS and other simulators.
  • Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687

Preferred Qualifications:

  • Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
  • DFT CAD development - Test Architecture, Methodology and Infrastructure
  • Test Static Timing Analysis
  • Post silicon validation using DFT patterns.
  • Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design

About Cisco

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79,500 employees
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Industry
Net Income
$10.1 billion
Founded
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