Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12 years of experience in design verification.
- Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience defining verification architectures, methodologies, and roadmaps for AI accelerators, High-Performance Computing or high-bandwidth networking silicon.
- Experience bridging the gap between Pre-Silicon verification (simulation and emulation) and Post-Silicon validation and correlation.
- Experience driving advanced verification methodologies.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Technical Lead, you will define how Google verifies the physical-layer Digital Signal Processing (DSP) pipelines powering our next-generation AI hardware accelerators. You will drive the shift toward Emulation and Post-Silicon Correlation, ensuring that our architectural reference models and pre-silicon simulations perfectly match the physical behavior of the high-speed silicon in our planetary-scale AI data centers.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $240000 - $333000 (USD) 25% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities- Design, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks.
- Build co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models.
- Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows.
- Author dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles.
- Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.
