Analog & Mixed-Signal ASIC Design Engineer

We are seeking an experienced Analog ASIC Design Engineer to join one of Tektronix’s design centers in Louisville, Colorado or Beaverton, Oregon. In this role, you will design innovative CMOS, BiCMOS, and HBT RF integrated circuits that are central to our next‑generation products. You will collaborate closely with an exceptional, cross‑functional team to deliver industry‑leading solutions using world‑class design tools.

Responsibilities

• Design and develop key analog and mixed‑signal building blocks for next‑generation ASICs using advanced design tools.
• Perform circuit simulations to optimize performance, robustness, and manufacturability.
• Conduct signal and system‑level analysis beyond the ASIC to ensure end‑to‑end performance.
• Characterize designs and/or develop comprehensive characterization plans.
• Partner with product line architects to evaluate power, cost, and performance trade‑offs at the system level and drive informed design decisions.
• Contribute to technical documentation and design reviews across the development lifecycle.

Minimum Qualifications

• BSEE or MSEE in Electrical Engineering
• 5+ years of hands‑on experience designing analog and/or mixed‑signal integrated circuits (e.g., amplifiers, PLLs, ADCs, DACs).
• Proficiency with modern ASIC design and verification tools.
• Strong foundation in analog and RF analysis prior to simulation.
• Experience with layout of critical analog/RF cells.
• Strong verbal and written communication skills, including technical documentation.
• Ability to collaborate effectively with professionals at all levels of the organization.
• Willingness to travel domestically on a limited basis.
• Strong interest in process technology trends and a commitment to continuous learning and improvement.
• Due to export control restrictions, candidates must be a U.S. Person (U.S. Citizen or Green Card holder).

Preferred Qualifications

• MSEE or PhD in Electrical Engineering
• 10+ years of experience in analog and/or mixed‑signal IC design.
• Experience designing, modeling, and optimizing phase-locked loop (PLL) architectures, including loop dynamics, phase noise, jitter performance, frequency synthesis, and mixed-signal implementation trade-offs.
• Experience characterizing designs in the lab and correlating silicon results with simulation.
• Experience in design/modeling high-frequency electronic components using 3D electromagnetic (EM) field solver like Ansys HFSS or Cadence EMX.
• Experience working effectively with remote, geographically distributed teams.
• Demonstrated ability to influence architectural and high‑level design decisions.