The candidate must have a strong background in analog and digital signal processing and must be able to leverage those skills in order to define architectures for the next-generation of touch-sensing and display ASIC's.
Responsible for develop arm based low level drivers and diagnostics test programs in c, perform soc bandwidth and power profiling study, define validation plan, implement automation tools, and support soc products to mass-production.
Responsible for soc design/integration, defining and creating clock/reset logic for the chip, coming up with full-chip pad ring, synthesis, equivalence check, linting/cdc analysis, and static timing analysis for multi-million gate socs targeted for voice assistant & multimedia applications.
The responsibilities for this position include functional verification at a block level, subsystem and usage of verification techniques such as constrained random testing, black box and white box testing concepts.
Responsibilities include design and specification of new capacitive sensing schemes, IC designs, and algorithms. Excellent communication skills, along with creativity in finding technical solutions, is essential for working in our fast paced R&D environment.
This role will be responsible for driving the relationship with Synaptics' partners with a particular focus on the AudioSmart solution. Recognizing the unique attributes and strengths of the Synaptics' solution, this person will develop relationships with decision-makers and influencers and uncover opportunities at key customers and partners, working closely with sales to close design opportunities and working closely with marketing to provide feedback on longer term product strategy.
Design GPIO and specialty pads for digital and mixed-signal applications; responsibility includes specification development, circuit design, layout and review, signal integrity analysis and simulation.