Innovate verification strategies for advanced CPU memory management units. Lead cross-functional collaboration to define risks, enhance verification quality, and solve complex challenges in high-performance out-of-order core architectures.

Lead high-performance CPU frontend verification, collaborating with architecture and design teams to innovate solutions. Drive strategies across verification planning, execution, and debug, enhancing methods and quality throughout the organization.

Shape the future of CPU-subsystem power-management verification by leading the planning, execution, and technical strategy to ensure quality and resiliency in complex SoC environments, directly impacting data-center-grade functionality and integration.

Drive innovation as you design advanced CPU and interconnect IP, leveraging RISC-V architecture to accelerate time-to-market and enhance hardware configurability within a dynamic engineering environment.

Drive innovation by architecting advanced hardware solutions in CPU design and interconnect IP, contributing to the acceleration of RISC-V adoption across various industries. Collaborate in a dynamic environment to enhance and deploy high-performance technologies.