Lead the charge in verifying complex cache-coherent interconnect subsystems, defining comprehensive strategies and methodologies to enhance verification quality while mentoring engineers and collaborating across multiple technical teams for successful integration.

Drive verification excellence by leading strategy for a scalable cache-coherent interconnect subsystem, orchestrating collaboration across teams to ensure quality and reliability in high-performance CPU and SoC designs.

Lead the charge in defining and executing verification strategies for a scalable cache-coherent interconnect subsystem in high-performance CPU and SoC platforms, while driving quality and cross-team collaboration.

Unlock your potential as a key hardware engineer, designing cutting-edge CPU and SoC power management solutions in a collaborative environment. Drive innovation in RISC-V architecture and enhance the agility of hardware development.

Drive innovation in CPU design by creating advanced power management, reset, and clocking solutions. Collaborate in a dynamic team to enhance RISC-V architectures, ensuring high quality and performance for next-gen SOC IP designs.