Empower the innovation of SoC/IP by ensuring bug-free silicon through comprehensive verification strategies and testing environments that enhance performance and reliability across design architectures and micro-architectures.
Optimize verification of RTL designs by developing UVM-based tests, engaging with design engineers, and debugging issues. Collaborate on coverage analysis to ensure robust design validation across multiple scenarios and specifications.
Join a dynamic team as a key leader driving marketing strategy and planning. Collaborate closely with executives to shape strategy, enhance planning processes, and coordinate efforts across diverse functions for impactful business outcomes.
Drive high-performance clock architecture projects end-to-end. Engage in clock planning, designing distribution circuits, and optimizing synchronization across multiple domains while ensuring signal integrity and reliability through rigorous simulations.
