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X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA; San Diego, CA, USA.
Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in managing functional verification for IPs and SoCs.
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience leading design verification of an SoC or large ASICs.
- Experience in collaborating effectively across organization and geo boundaries to build relationships and import/export ideas to achieve a broader organizational goal.
- Experience in driving cross-functional teams for high quality tape-outs.
- Deep technical expertise in different verification techniques and methodologies including formal, GLS, UPF based power simulations, UVM and C based testing, to achieve bug-free Silicon in complex SoCs.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Act as the primary point of contact for IP and SoC functional verification for cross functional teams.
- Coordinate with architecture, design teams, Sival and SW teams in defining the overall verification strategy of our SoCs.
- Set the goal and own verification methodology for multiple chips.
