Job Description:

The successfulcandidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industrys cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the worlds information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industrys technology leadership.

An opening exists for Tech Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchips Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you won't just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment you'd like to participate in, we'd like to hear from you!

As a Staff Design Engineer, your job will entail the following:

• Own design planning and construction of pad rings, bump patterns, ensuring alignment with package and system-level constraints.

• Develop, implement, and maintain IO connectivity, pad ring definitions, and bump pattern designs throughout the design cycle.

• Generate and validate physical design handoff deliverables including pad ring DEF files, Verilog netlists, bump maps, and associated implementation data for downstream teams.

• Ensure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.

• Collaborate with Architecture, Product Design, Internal IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to align on IO/package requirements and resolve technical issues.

• Support Verification, Emulation, ASIC validation, and silicon debug efforts by analyzing IO-related issues and driving design improvements.

Requirements/Qualifications:

• B.S degree in electrical engineering with 12+ years related experience.

• Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.

• Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL).

• Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent); specific tool experience is valuable but not mandatory.

• Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand-off).

• Understanding of Foundation and Hard IP related views including RTL, lef and liberty

• Working proficiency in flow automation and scripting using tcl and/or python

• Excellent analytical, communication (written and verbal), and documentation skills.

Preferred qualifications:

• M.S degree in electrical engineering

• Basic understanding of DFT methodologies mainly JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation for including post-silicon bring-up and debug flows for SoC IO validation

• Exposure to RTL compilation and Synthesis flow including understanding of Verilog/System Verilog is desirable

• Working knowledge of Industry standard Project management, versioning and tracking tools e.g. SVN, JIRA.

Travel Time:

Pay Range: