Job Description:The successful candidate will be responsible for system-level Analog Mixed-Signal (AMS) verification and Power Integrity (PI/SI) for next-generation SoCs and chiplet-based platforms, integrating analog IP in mature nodes with advanced digital nodes (e.g., 12nm and beyond).
Key Responsibilities - Lead/contribute to sub-system and chip-level AMS and SPICE simulations for complex SoCs and multi-die (chiplet) architectures
- Drive AMS verification across chiplet boundaries, including cross-node integration (mature analog + 12nm digital)
- Collaborate closely with SoC design, architecture, analog, and advanced-node digital implementation teams
- Review and understand SoC specifications, IO subsystems, and die-to-die interface requirements
- Plan and execute AMS/SPICE simulation strategies, including full-chip and chiplet-level verification.
- Perform PI/SI simulations covering:
- Die pad ring
- Package and interposer (chiplet-based designs)
- PCB interfaces (as applicable)
- Analyze power integrity and signal integrity across chiplet interfaces and multiple power domains
- Develop and enhance AMS and PI/SI methodologies and flows for multi-die/chiplet systems
- Partner with validation teams on silicon bring-up, debug, and simulation-to-silicon correlation
Requirements/Qualifications:- Bachelor's/Master's degree in electrical engineering or equivalent with 14+ years of experience.
- Proven experience in AMS verification for advanced SoCs, including exposure to 12nm nodes or beyond
- Solid understanding of cross-domain interactions and multi-voltage/power domains
- Hands-on experience with industry-standard tools:
- Cadence (Virtuoso, Spectre, AMS Designer)
- Questa ADMS / Symphony
- HSPICE or equivalent
- Experience in silicon debug and correlation of simulation results with silicon behavior
- Ability to analyze and interpret chip-level electrical specifications and IO requirements.
- Strong communication skills with the ability to work effectively in a global, cross-functional environment
Preferred- Experience with chiplet architectures or multi-die system integration
- Exposure to die-to-die interfaces and advanced node (12nm and beyond) integration challenges
- Experience in circuit-level debug and modeling
Travel Time:0% - 25%
Physical Attributes:Hearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:90% Sitting, 10% Standing/Walking
