Job Details:Job Description:Join the Logic Technology Development (LTD) organization, a powerhouse of process technology innovation driving Intel's IDM 2.0 strategy to exceed the aspirations of our global customers. We are seeking a visionary Principal Engineer to lead the charge in Intel's foundry revolution, serving as a strategic technical architect and executive partner in guiding our most critical customers through the entire product development lifecycle. In this leadership capacity, you will orchestrate multidisciplinary strategies spanning device engineering, product integration, and yield analysis to steer customers from critical design tape-out and pre-silicon evaluation through to NPI silicon qualification. Furthermore, you will define the strategic roadmap for Far Back End (FBE) expertise in test, bump, and assembly, ensuring a seamless, scalable transition into High Volume Manufacturing (HVM) and volume ramp. This high-impact role provides executive technical leadership, engages directly with customers, drives the success of multi-billion-dollar programs, and helps shape the future of the global semiconductor industry in the AI innovation era.
What you will do:
We are seeking an elite level of semiconductor expertise to drive the strategic direction of foundry technology development. Based on your leadership experience, your focus will include:
Yield Engineering and Performance Optimization
- Strategic Yield / Performance Governance: Establish the overarching yield strategy and governance framework for the foundry product lifecycle, ensuring a seamless transition from design to HVM.
- Roadmap Architecture: Define and steer the long-term yield / performance goals, technology features and roadmaps for foundry customer silicon in alignment with Intel Business Group, Technology Development, Design Technology Platform.
- Systemic Loss Mitigation: Lead high-level strategic initiatives to identify and eliminate systematic and parametric yield detractors, directing cross-functional teams across Process Integration, Device Engineering, and Defect Metrology.
- Predictive Modeling Strategy: Oversee the development of advanced predictive models, using AI/ML, for parametric and defective loss, ensuring projection accuracy for test chips and high-volume products.
- Metric Correlation Frameworks: Define the standards for correlating inline process metrics with end-of-line yield and performance to institutionalize better process control across the organization.
Product Integration and NPI Execution
- NPI Strategic Leadership: Direct the execution of New Product Introduction (NPI), overseeing wafer lot progress, skew split strategy, and targeting for flagship customer products.
- Device Performance Strategy: Lead the analysis of device performance and variability for logic, SRAM, and emerging device types to ensure industry-leading specifications.
- Experimental Design Oversight: Architect complex Design of Experiments (DOE) and skew split plans to optimize product health and accelerate time-to-market.
- Technology Compliance: Ensure organizational adherence to critical customer technology metrics, including fab process yield, E-Test (ET), WAT/C, and Cp/Cpk.
Design Enablement and PDK Management
- PDK Strategic Vision: Drive the vision for high-quality Process Design Kits (PDKs), ensuring they are optimized for customer success through rigorous validation of metrology and yield data.
- Simulation Standards: Oversee the Sil2Sim (Silicon-to-Simulation) correlation frameworks and layout effect assessments to reduce design iterations.
- Governance and Risk Management: Chair or provide executive guidance to the Waiver Review Board (WRB) to assess and mitigate risks associated with DRC violations.
- IP Ecosystem Development: Lead the strategy for intellectual property (IP) design activities, ensuring robust design rules and seamless mask tape-out execution.
Cross-Functional Interface and Customer Management
- Executive Technical Liaison: Serve as the primary executive process expert and strategic interface between external foundry customers and internal leadership.
- Strategic Communication: Deliver high-level technical readouts and strategic health reports on process development to Intel senior management and C-suite customer stakeholders.
- POR Accountability: Own the LTD customer technology deliverables and the product Plan of Record (POR), ensuring alignment with corporate execution goals.
- Escalation Management: Act as the final point of resolution for critical technical blockers, managing the organizational response to complex customer requests.
Operational Excellence and Ecosystem Development
- Foundry Ecosystem Design: Define and institutionalize best-in-class foundry customer service practices and IP/data management systems to scale the business.
- Organizational Standardization: Drive the transformation of operational systems and methodologies to improve global efficiency and standardization across fab and development teams.
- Continuous Improvement (CIP) Leadership: Lead the central TD factory teams in auditing and improving product yield/performance commits through the Continuous Improvement Program.
• End-to-End Integration: Architect the integration between development, assembly, and test teams to ensure a cohesive flow from wafer to final package.
Qualifications:Minimum Qualifications
- Master's Degree with 13+ years of experience OR PhD Degree with 10+ years of industry experience. Accepted degrees in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science discipline.
- The years of related work experience listed above must be in the field in at least one of the following areas: Semiconductor integration, device engineering, or yield engineering.
Preferred Qualifications:
- 10+ years of direct semiconductor yield and performance analysis and strategic engineering leadership.
- Proven track record in yield pareto construction, modeling, projection, and the development of long-term yield roadmaps.
- Proven track record in process integration, device engineering, performance projection, and the development of long-term performance roadmaps.
- Extensive experience leading a foundry team or managing high-level foundry customer collaborations.
- Expertise in interpreting complex product data (inline, e-test, and SORT) to drive organization-wide solutions.
- Deep knowledge of inline inspection methods and SORT programs.
- Deep experience collaborating with fabless design houses on product development cycles.
- Proven history of executive-level customer service and strong customer orientation in a foundry environment.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, Oregon, Hillsboro
Additional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
