The application window is expected to close on: 01/28/2027
This position requires that you live within commuting distance of our Milpitas, CA office and commute to the lab 5 days per week.
Your Impact- As a Senior Technical Lead Hardware Board Design Engineer, you will be a recognized expert who shapes multi-year hardware architecture, design standards, and technical strategy for major networking products. You will lead high-impact, cross-functional initiatives, resolve the most complex technical problems, and influence senior leaders through clear engineering judgment and compelling technical decisions. This is an individual contributor role with enterprise-level influence; it does not require people management.
- Define long-term hardware architecture, power-delivery strategy, design standards, and technology roadmaps for high-performance networking systems.
- Lead major, multi-disciplinary hardware initiatives from early concept through product release and customer delivery.
- Act as a senior escalation point for novel or high-risk architectural, signal integrity, power integrity, reliability, field, and manufacturing issues.
- Develop and communicate technical strategies that align multiple business units and engineering disciplines.
- Establish reusable methods, constraints, verification practices, and quality standards for board design.
- Guide senior engineers and technical leaders through architecture reviews, design tradeoffs, and complex investigations.
- Represent hardware engineering in executive reviews, strategic supplier discussions, standards activities, and selected external technical engagements.
- Anticipate industry and technology shifts and recommend investments in future hardware capabilities.
- Drive decisions using simulations, laboratory evidence, product data, and a clear understanding of business impact.
Minimum Qualifications- Bachelor's degree in Electrical Engineering or Computer Engineering and 11+ years of experience, or Master's in Electrical Engineering or Computer Engineering and 7+ years of related experience, or PhD in Electrical Engineering or Computer Engineering and 4+ years of related experience.
- End-to-End System Design: Experience in hardware board design and system architecture-taking products from concept through production-for high-performance systems, including PCIe, Ethernet, DDR, SerDes, and advanced thermal/EMI management.
- Technical Validation & Tools: Experience with high-speed digital design, signal and power integrity, power distribution, and reliability testing, supported by hands-on use of Cadence design tools and advanced lab instrumentation (oscilloscopes, logic/spectrum analyzers).
- Strategic Leadership & Delivery: Experience leading complex, multi-site, and cross-functional engineering initiatives, partnering with silicon vendors and contract manufacturers to solve high-impact, ambiguous technical challenges at scale.
Preferred Qualifications- Systems Architecture: Experience with advanced networking systems, ASICs, FPGAs, high-speed memory, multi-gigabit SerDes, and advanced packaging.
- Specialized Technologies: Experience in co-packaged/near-packaged optics, signal/power integrity budget analysis, ultra-high-speed signaling, and next-generation power delivery.
- Technical Proficiency: Hands-on experience with Cadence (Concept/Allegro), HyperLynx, ANSYS, Keysight ADS, and advanced lab equipment (VNA, TDR, high-bandwidth oscilloscopes, protocol analyzers).
- Automation: Experience with creating test scripts using Python to streamline validation and design tasks.
- Problem-Solving: Analytical, methodical approach to decomposing complex issues, evaluating empirical evidence, and documenting clear, actionable conclusions.
- Collaboration: History of working effectively within cross-functional teams to drive initiatives forward.
- Leadership & Influence: History of influencing senior technical and business leaders across organizational boundaries, underpinned by exceptional written, verbal, and executive-level communication skills. Dedicated to driving excellence through the mentorship of senior engineering talent.
- Innovation & Industry Impact: A record of delivering large-scale products and technical innovations, evidenced by a history of patents, influential publications, and active standards participation. Committed to advancing the field through strategic thought leadership.
- Education: Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
Message to applicants applying to work in the U.S. and/or Canada:The starting salary range posted for this position is $194,600.00 to $285,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco's policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$194,600.00 - $328,600.00
Non-Metro New York state & Washington state:
$179,000.00 - $294,000.00
* For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
