Minimum qualifications:- Bachelor's degree in Mechanical Engineering, Electrical Engineering, a relevant technical field, or equivalent practical experience.
- 10 years of experience in SoC thermal architecture and system-level power modeling.
- Experience with Computational Fluid Dynamics (CFD), compact RC modeling (specifically Ansys Icepak) within a silicon design environment.
- Experience with SoC design, IC packaging, Power, Performance, and Area (PPA) constraints, thermal-aware floorplanning, and multi-die heat dissipation.
- Experience with system-level power and thermal modeling, and building modeling flows and automation toolchains using Python or MATLAB
Preferred qualifications:- Ph.D. in Mechanical Engineering, Electrical Engineering, or a closely related field.
- 8 years of specialized experience focusing specifically on the end-to-end optimization of thermal, power, and performance metrics in heavy-compute or AI-first silicon.
- Excellent communication skills with a track record of driving alignment across global, cross-functional engineering organizations.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of the Tensor Silicon Engineering team scaling mobile AI capabilities, you will guide system-level thermal architecture in Mountain View. With power density outpacing node scaling in heavy-compute and agentic AI workloads, thermal dissipation is a key performance constraint. In this role, you will help shift from reactive, component-level thermal management to proactive power-thermal co-optimization, balancing transient peak power demands with steady-state thermal design power (TDP) and enclosure temperature limits.
You will serve as the primary technical interface between Silicon Power Technology and product hardware teams. You will correlate silicon Power, Performance, and Area (PPA) metrics with system-level thermal boundaries to define sustained performance envelopes. Your focus will be architecting the SoC Thermal Budget and mitigation policies, establishing the power allocation frameworks required to execute high-concurrency AI workloads while maintaining junction temperature (Tj) safety margins and device ergonomic limits.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Collaborate with product design teams on thermal integration and optimization of SoCs in the system.
- Lead Camera features execution, development and roadmap within thermal constraints.
- Develop advanced thermal modeling and simulation capabilities to drive improved user experience.
- Outline and Deliver end-to-end validation of thermal KPIs.
- Act as a technical resource with Silicon and Platform thermal organizations.
