The Staff/Principal Engineer - HBM Design for Test (DFT) is a senior technical contributor responsible for defining, deploying, and sustaining best-in-class DFT solutions across HBM core die and base die spanning multiple HBM families with a primary focus on logic die MBIST support and architectural definitions along with implementation strategies. This role emphasizes DFT architecture, specification ownership, multi-functional alignment, and program support, supported by strong technical expertise to ensure solutions are robust, scalable, and manufacturable. The role includes close partnership with DFT Verification to ensure feature completeness, coverage, and readiness for tape-out and silicon bring-up. Key Responsibilities • Ensure DFT solutions enable high-quality, low-cost, and manufacturable HBM products • Define, implement, and document logic die MBIST architectures, including controller interaction, access mechanisms, sequencing, and broadcast behavior through high speed logic path design techniques. • Own test definitions and DFT entry flows supporting MBIST, logic test, interface test, and debug use cases including customer specified modes of operation. • Partner with logic and SoC architects to ensure DFT features are well-integrated, scalable, and generation-over-generation extensible • Support RTL debug and functional verification for DFT and MBIST related features through the use of Verilog and analog simulation tools. • Assist in defining checks, assertions, and coverage expectations related to logic die test functionality. • Work with APR teams to support physical implementation of DFT and MBIST logic including: - Timing closure for test paths and control logic - Evaluation of clocking, reset, and scan/MBIST routing impacts - Review of congestion, power, and area tradeoffs related to DFT features • Provide guidance on DFT-friendly floorplanning and implementation practices, especially for high-fanout or broadcast test structures along with providing scripts to improve efficiency where applicable. • Support late-stage implementation and signoff debug related to DFT timing, connectivity, or integration issues • Serve as the DFT and MBIST point of contact for assigned programs or functional areas • Contribute to documentation, knowledge sharing, and training within the DFT and design groups. • Mentor junior engineers and support technical skill development within assigned areas Minimum Qualifications: • Bachelor's degree in Electrical Engineering or related field (Master's preferred) • 5+ years of experience in design-for-test, logic test, or related SoC/ASIC design roles • Strong understanding of MBIST fundamentals, memory architectures, and logic test concepts. • Working knowledge of memory architectures (HBM or DRAM preferred) • Experience influencing DFT requirements, specifications, and verification expectations Preferred Qualifications: • Strong multi-functional collaboration skills, including work with verification organizations • Exposure to IEEE 1500 / DFT access mechanisms / broadcast test concepts • Experience supporting first silicon, qualification, or high-volume manufacturing debug Clear written and verbal communication skills