Micron Technology

Staff Physical Design Engineer, HBM

Micron Technology • $130K — $155K *
Richardson, TX 75080In-Person
Consumer Technology
5 - 7 years of experience
Today
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Job Overview by Ladders

Qualifications

  • 7+ years of experience in digital physical design or related field
  • Bachelor's degree in Electrical Engineering; Master's preferred
  • Strong knowledge of RTL-to-GDSII design flow
  • Experience with full-chip integration and partitioning
  • Proficient in scripting/programming (TCL, Python, etc.)
  • Understanding of low-power architectures and power integrity analysis
  • Ability to effectively communicate and collaborate in cross-functional teams

Responsibilities

  • Lead physical design from netlist to GDSII, covering floorplanning to signoff
  • Leverage AI-Enabled tools within the design flow for efficiency
  • Drive timing closure across multiple scenarios using STA tools
  • Analyze and fix timing, power integrity, and congestion challenges
  • Refine power grids and clocking strategies for optimal performance
  • Collaborate with RTL designers on micro-architecture and constraints early on
  • Implement low-power techniques such as power gating and multiple domains
  • Validate physical designs against verification standards
  • Drive ECOs to achieve design performance targets
  • Automate workflows using scripting for productivity enhancements
  • Interface with EDA vendors to troubleshoot and improve design methodologies

Benefits

  • Health, dental, and vision insurance
  • 401(k) retirement plan with company match
  • Flexible working hours and remote work options
  • Employee assistance programs
  • Opportunities for professional development and further education
  • Work on cutting-edge technology in a collaborative environment
Full Job Description
Micron's High-Bandwidth Memory (HBM) Digital Design organization is seeking a Digital Physical Design Engineer to drive backend implementation of high-performance, low-power digital logic used in advanced memory products. This role spans backend implementation from Netlist to GDSII, with a strong focus on timing closure, power integrity, and manufacturability in advanced process technologies. The successful candidate will work closely with RTL, DFT, CAD, and verification teams to deliver high-quality physical designs, contribute to methodology improvements, and help push performance, power, and area (PPA) targets in complex, multi-hierarchy designs.

Key Responsibilities:
  • Own and execute physical design implementation from synthesized netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical signoff
  • Utilize AI-Enabled tools in the Netlist to GDS flow
  • Perform and drive timing closure across multiple modes, corners, and scenarios using industry-standard STA tools
  • Analyze and resolve congestion, timing, IR drop, EM, and power integrity issues
  • Develop and refine floorplans, power grids, and clocking strategies for high-performance designs
  • Work with placement and timing closure of custom analog hard IP macros in a digital-on-top design flow
  • Collaborate closely with RTL designers to influence partitioning, constraints, and micro-architecture decisions early in the design cycle
  • Implement and validate low-power design techniques, including multiple/isolated power domains, power gating, and UPF/CPF-based power intent
  • Execute physical verification (DRC/LVS/ANT/DFM) and support signoff flows
  • Drive functional and timing ECOs as needed to meet design targets
  • Use scripting and automation (TCL, Python, etc.) to improve productivity, quality, and flow robustness
  • Interface with EDA vendors and internal CAD teams to debug tool issues, evaluate new tools and functions, and improve physical design methodologies.


Required Qualifications
  • Strong understanding of the RTL-to-GDSII physical design flow particularly floorplanning, place & route, clock distribution, and timing analysis and closure using standard EDA tools and advanced process technologies
  • Experience with full-chip integration, partitioning, and budgeting
  • Solid understanding of power, performance, and area tradeoffs
  • Knowledge of low-power architectures, including DVFS, power gating, and multi-voltage designs
  • Proficiency in scripting/programming (TCL , Python, Perl, Shell scripting)
  • Strong problem-solving skills and ability to debug complex physical design issues
  • Effective communication skills and ability to work in a cross-functional team environment
  • Experience in validating Power Distribution Network (PDN), IR/EM


Preferred Qualifications:
  • Experience with advanced technology nodes
  • Experience with high-frequency, high-density designs and complex clocking schemes
  • Familiarity with memory, HBM, or datapath-intensive designs
  • Understanding of device physics and process-technology impacts
  • Experience in the 3D-IC technology, methodology, and advanced packaging and thermal considerations


Education and Experience:
  • Required: Bachelor's degree in EE with good understanding of computer architecture and 7+ years experience in related field
  • Desired: Master's degree in EE / CE with 5+ years experience in related field

About Micron Technology

Micron Technology Careers

Join the vibrant team at Micron Technology, a leader in memory and storage solutions, and propel your career into the future of technology. At Micron, we are committed to fostering a culture of diversity and innovation, offering a range of job opportunities that encourage professional growth and leadership development.

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At Micron Technology, you will collaborate with some of the brightest minds in the industry, working on groundbreaking projects that redefine how the world uses information to enrich life. Our team is dedicated to leading through a unique position in the marketplace, at the intersection of technology, industry expertise, and digital innovation.

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Learn more about Micron Technology
Size
43,000 employees
Market Cap
$53.7 billion
Industry
Manufacturing & Automotive
Net Income
$2.9 billion
Founded
1978
5 Year Trend
+8.6%
Revenue
$22 billion
NASDAQ
MU
* Ladders Estimates

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