Micron Technology

Staff Physical Design Engineer, HBM

Micron Technology$130K — $155K *
Consumer Technology
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 7+ years of hands-on experience in advanced-node physical design.
  • Tape-out experience on HBM, DRAM, or large memory-centric designs.
  • Deep expertise in floorplanning, timing closure, power integrity, and physical signoff.
  • Demonstrated ability to lead complex designs through silicon bring-up.
  • Expert-level experience with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler.
  • Proficient in PrimeTime STA and familiar with Calibre DRC/LVS.

Responsibilities

  • Drive physical design for HBM base die and/or memory dies from netlist through GDSII.
  • Own floorplanning and power planning for high macro density HBM designs.
  • Define HBM-specific architecture, including PHY placement and TSV regions.
  • Make architecture-level tradeoffs to optimize design performance.
  • Assist in power delivery network design for high current density environments.
  • Drive closure on IR drop, EM, and thermal issues across operating modes.
  • Ensure foundry reliability compliance and manage timing closure across corners.

Benefits

  • Mentorship opportunities for both junior and senior engineers.
  • Engagement in leading-edge HBM design projects.
  • The chance to influence and shape the memory architecture and interface definitions.
  • Collaborative work environment with cross-functional teams.
  • Opportunities for advancement and contribution to design innovations.
Full Job Description
Responsibilities will include, but are not limited to:
  • Drive end-to-end physical design for HBM base die and/or memory dies from netlist through GDSII.
  • Own floorplanning, power planning, placement, CTS, routing, and signoff for HBM designs with very high macro density.
  • Define and drive HBM-specific physical architecture, including channel partitioning, PHY placement, and TSV keep-out regions.
  • Work with design to make architecture-level tradeoffs to optimize bandwidth, latency, power, and yield.
  • Assist power delivery network (PDN) design for extremely high current density environments.
  • Drive IR drop, EM, and thermal closure across all operating modes.
  • Ensure compliance with foundry reliability rules, including EM lifetime, via density, and TSV stress considerations.
  • Own timing closure across corners for high-speed internal logic and HBM PHY interfaces.
  • Partner with clocking and PHY teams on clock distribution, skew control, and jitter sensitivity.
  • Collaborate with packaging teams on 2.5D interposer-based integration and HBM stack interfaces.
  • Ensure physical alignment of micro-bumps, TSVs, RDLs, and keep-out zones.
  • Own physical signoff readiness: STA, IR/EM, SI, DRC, LVS, density, and reliability.
  • Leveraging AI in LVS/DRC fix automation throughout the design phase.
  • Lead ECO strategies, including late-stage timing and power fixes.
  • Act as a key technical voice in tape-out and executive design reviews.
  • Partner with memory design, PHY, RTL, synthesis, DFT, SI, packaging, and test teams.
  • Influence memory architecture and interface definitions to improve physical feasibility.
  • Mentor senior and junior engineers; establish HBM-specific PD best practices and methodology.
  • Drive flow improvements, automation, and reuse across HBM generations.

HOW TO QUALIFY
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 7+ years of hands-on experience in advanced-node physical design.
  • Proven tape-out experience on HBM, DRAM, or very large memory-centric designs.
  • Deep expertise in:
    • Floorplanning and hierarchical PD
    • Timing closure and STA fundamentals
    • Power integrity (IR/EM) and thermal awareness
    • Physical signoff for advanced technologies
  • Demonstrated ability to lead complex designs through successful silicon bring-up. Strong problem-solving skills and ability to work independently on complex designs.
  • Expert-level experience with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler.
  • Strong proficiency in PrimeTime STA.
  • Experience with RedHawk, or equivalent PI tools.
  • Familiarity with Calibre DRC/LVS and advanced foundry signoff flows.
  • Experience with FinFET and sub-10nm nodes strongly preferred.

Preferred Qualifications
  • Direct experience with HBM2E / HBM3 / HBM3E products.
  • Understanding of TSV-based designs and micro-bump layouts.
  • Experience with die-to-die interfaces and wide parallel buses.
  • Knowledge of advanced packaging (2.5D interposer, chiplets).
  • Strong Tcl / Python scripting for PD flow automation.

About Micron Technology

Micron Technology Careers

Join the vibrant team at Micron Technology, a leader in memory and storage solutions, and propel your career into the future of technology. At Micron, we are committed to fostering a culture of diversity and innovation, offering a range of job opportunities that encourage professional growth and leadership development.

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Learn more about Micron Technology
Size
43,000 employees
Market Cap
$53.7 billion
Industry
Net Income
$2.9 billion
Founded
1978
5 Year Trend
+8.6%
Revenue
$22 billion
NASDAQ

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