Company:Qualcomm Canada ULC
Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:You will lead and drive
physical design implementation for complex, large-scale retimer-class and full-reticle ASIC products in advanced technology nodes. This role requires strong technical leadership to synthesize ambiguous requirements, drive execution across cross-functional teams, and deliver high-quality silicon meeting aggressive power, performance, and area (PPA) targets.
Replacement PositionWhat You'll Do- Lead and execute end-to-end Physical Design flow for SoC and retimer ASICs, including:
- Floorplanning
- Clock Tree Synthesis (CTS)
- Placement & Routing
- Power Delivery Network (PDN)
- Timing analysis and closure
- Plan and implement full-chip or hierarchical designs, including full-reticle-scale integration
- Drive timing closure across all corners and modes (MMMC), including SI-aware optimization
- Perform and review physical verification checks:
- DRC, LVS
- Design-for-manufacturability (DFM)
- Design-for-yield (DFY)
- Collaborate with cross-functional engineering teams (front-end, analog/SerDes, DFT, packaging, silicon validation) to ensure design convergence and tapeout readiness
- Lead integration of high-speed SerDes macros and mixed-signal IP, ensuring robust floorplan and signal integrity alignment
- Drive IR/EM closure, power optimization, and congestion mitigation for large die designs
- Provide schedules, risk assessment, and execution tracking to drive successful silicon tapeouts
- Act as a strong technical contributor in design reviews and project meetings, influencing architecture and implementation decisions
- Develop and improve physical design methodologies and flows to enhance efficiency and scalability
What You'll Need: - Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of experience, OR
Bachelor's degree and 4+ years of progressive experience in ASIC Physical Design or related domain - Strong experience with:
- End-to-end ASIC Physical Design flow
- Timing closure and signoff methodologies
- Physical verification flows
- Hands-on expertise in industry-standard EDA tools (e.g., Cadence Innovus / Synopsys ICC2)
- Solid understanding of:
- Power delivery and reliability (IR/EM)
- Clocking architectures and CTS
- Large-scale SoC integration challenges
Preferred Qualifications- Experience with high-speed SerDes / retimer designs (PAM4-class signaling)
- Experience with full-reticle or near-reticle SoC implementation
- Familiarity with multi-die / chiplet / advanced packaging architectures
- Exposure to data center, networking, or optical connectivity ASICs
- Strong scripting and automation skills (Python, Tcl)
Key Competencies- Proven ability to lead complex PD execution in high-pressure tapeout environments
- Strong analytical and problem-solving skills with attention to detail
- Ability to synthesize ambiguous or conflicting requirements into execution plans
- Effective collaboration across global, cross-functional engineering teams
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Pay range and Other Compensation & Benefits:$124,200.00 - $174,200.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.
If you would like more information about this role, please contact Qualcomm Careers.
