Staff Digital Verification Engineer

Monolithic Power Systems, Inc.

$130K — $160K *
Technical Services
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • PhD/BS/MS in Electrical Engineering focused on Digital Design/VLSI coursework.
  • 5+ years of experience in design and verification of ASIC or FPGA.
  • Strong knowledge of the ASIC development process and digital design techniques.
  • Proficient in Verilog, System Verilog, UVM, and automated regression testcase development.
  • Experience with programming/scripting in C/C++, shell, Perl, TCL, Python, etc.
  • Solid knowledge of the complete Digital Design Flow, including RTL Verification and Power Estimation.
  • Excellent communication skills, with a strong emphasis on teamwork.

Responsibilities

  • Develop test plans, test benches, and automate test cases for digital verification.
  • Support design debugging efforts effectively.
  • Lead digital design of ASIC or FPGA from concept to implementation.
  • Oversee synthesis, timing closure, and formal verification processes.
  • Create and manage automation scripts for design and verification tasks.
  • Estimate time and manage tasks to meet project schedules.

Benefits

  • Opportunity to work on innovative products in a fast-growing tech sector.
  • Access to a collaborative and supportive work environment.
  • Potential for involvement in projects that span various applications, enhancing career development.
  • Location in San Jose, CA, a prestigious tech hub with abundant resources and networking opportunities.
Full Job Description

Job Description:

The candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other key skills include technical/project leadership, documentation, RTL design knowledge, and backend flow and tools knowledge. Candidate will be expected to lead design, verification, and be technical focus on one or more devices and/or sections. Candidate will also be expected to support pre/post-silicon design validation and support Design/ATE/Application & Systems group.

MPS products include DDR devices, switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as broadband modems, notebooks, cell phones, telecom, fiber optics, digital camera, automobile and network equipment.

Essential Functions:

  • Digital Verification: Development test plans, test benches and automated test cases
  • Support Design Debug
  • Digital Design (RTL design): ASIC or FPGA from concept to implementation
  • Knowledge and/or responsibility in synthesis, timing closure, and formal verification.
  • Create scripting to support design and verification automation
  • Estimate and manage time/tasks completion to target schedule

Qualifications:

  • PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
  • 5+ years’ experience in design plus verification of ASIC or FPGA
  • Strong knowledge of ASIC development process and digital design techniques
  • Proficient in standard DV languages (Verilog, System Verilog, UVM) and automated regression testcase development, and reporting/tracking coverage metrics.
  • Experience with programming, scripting and automation languages (C/C++, shell, Perl, TCL, Python, etc.,).
  • Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
  • Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.
  • Good written/verbal communication skills and strong teamwork/collaboration.
  • Experience with the following is desired:
    • Embedded designs and/or firmware development
    • JEDEC, Automotive FuSA and ASIL Standards
    • Knowledge of DDR, power management industry/applications
    • I2C, I3C, SPI, USB, PMBUS
    • GITLab

Location:

San Jose, CA

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