Advanced Micro Devices, Inc

STA/Constraints Engineer

Advanced Micro Devices, Inc • $120K — $160K *
Santa Clara, CA 95051In-Person
Technical Services
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • 5-7 years of industry experience in static timing analysis and constraints
  • Expert in using industry-standard PD tools like SNPS PT/GCA
  • Solid understanding of DFT timing concepts and Place and Route flows
  • Proficient in scripting with Perl/TCL/Shell/Python
  • Strong verbal and written communication skills
  • Experience with large digital ASIC projects
  • Familiarity with lower power design methodologies

Responsibilities

  • Own delivery of SOC designs from timing constraints to signoff
  • Collaborate with SOC Architecture for timing target goals
  • Ensure accurate setup of clock design requirements in SDC
  • Analyze timing margins and collaborate with methodology teams
  • Meet project requirements and deadlines for timing closure
  • Work with CAD and EDA vendors to enhance timing methodologies
  • Conduct CDC/lint checks and support timing closure efforts

Benefits

  • Comprehensive health insurance
  • Retirement savings plan with company match
  • Paid time off and holidays
  • Employee wellness programs
  • Professional development opportunities
Full Job Description
THE ROLE:

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

KEY RESPONSIBILITIES:

  • Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
  • Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
  • Understanding clock design requirements and making sure they are correctly set up in SDC.
  • Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
  • Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
  • Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
  • Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
  • Work on SDC development, STA (Static Timing) analysis, shift left of timing closure, CDC (Clock Domain Crossing).

PREFERRED EXPERIENCE:
  • Industry experience in STA, constraints, timing signoff and physical design
  • Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
  • Good experience and understanding of DFT timing concepts, MBIST, Top level clock -implementation, Place and Route flows -floorplanning and placement, CTS and Route.
  • Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
  • Excellent presentation and inter-communication skills.
  • Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
  • Experience with physical design is a plus.
  • Has Synthesis or physical implement experience.
  • Experience with lower power design methodology.
  • Good English skills on talking, presentation and writing documents.
  • Good communication and strong sense of responsibility, task scheduling, and time management.

ACADEMIC CREDENTIALS:
  • Bachelor/Master's degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

LOCATION: Santa Clara, CA

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This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

Advanced Micro Devices, Inc. Careers

Join the innovative forefront of technology with a career at Advanced Micro Devices, Inc. (AMD), a leader in semiconductor development. As part of our global team, you will contribute to an organization renowned for its dedication to innovation, leadership, and diversity in the tech industry.

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Join a team of over 12,000 dedicated professionals at the intersection of technology, industry expertise, and digital innovation. At AMD, you will work on groundbreaking projects that shape the future of computing and graphics. Our collaborative environment encourages networking and the sharing of ideas across teams and disciplines.

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AMD is committed to the development of its employees. We offer robust training programs, including leadership development and diversity training, to ensure our team is equipped for both current challenges and future opportunities. Our benefits package is designed to support the well-being and financial security of our employees and their families.

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Manufacturing & Automotive
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ
AMD
* Ladders Estimates

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