Job Area:Engineering Group, Engineering Group > Hardware Engineering
General Summary:The Reliability Engineering organization leads the definition and execution of reliability strategy for advanced semiconductor technologies, ensuring robust qualification and technology certification across devices, packages, and systems. The team applies deep expertise in device and interconnect reliability physics-including BTI, TDDB, HCI, electromigration, self-heating, and wear-out mechanisms-to assess design and process robustness for complex SoCs and advanced packaging architectures (2.5D/3D, TSV, chiplets). Working cross-functionally with design, process, test, product, and program teams, the organization anticipates and mitigates reliability risks across the full product lifecycle while balancing performance, power, quality, schedule, and business objectives. As a technical authority, the team establishes scalable reliability best practices, provides expert judgment on critical trade-offs and EM waivers, mentors engineers, and communicates clear reliability status and risk insights to senior leadership.
Minimum Qualifications:• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Responsibilities
- Define foundry qualification reliability requirements, and execute to tech certification for complex designs and advanced technologies.
- Lead reliability strategy and execution for high-impact products and programs, spanning devices, packages, and systems.
- Perform and guide advanced reliability analysis, including aging, wear-out, electromigration, and other mechanism-based modeling, to assess design and process robustness.
- Anticipate, identify, and mitigate non-obvious reliability risks across the full product lifecycle.
- Drive cross-functional alignment with design, process, test, product, and program teams to meet aggressive schedules without compromising quality.
- Establish and improve organizational reliability processes and best practices that scale to future technology generations.
- Provide expert technical judgment on critical reliability trade-offs, balancing performance, power, quality, schedule, and business considerations.
- Mentor and develop engineers; serve as a trusted technical authority and advisor for reliability across the organization.
- Communicate reliability status, risks, and strategic recommendations clearly to senior leadership and executive stakeholders.
Qualifications- 10 - 15 years of industry experience in semiconductor reliability engineering, technology development, or product qualification, supporting advanced CMOS nodes (Planar, FinFET, GAA).
- Deep expertise in intrinsic device and interconnect reliability physics and failure mechanisms, including BTI, TDDB, HCI, electromigration (EM), self-heating effects, and MOL/BEOL wear-out.
- Hand-on experience in designing reliability test structures for test-chips, reliability test structure measurements and interpreting complex reliability data from various reliability mechanisms like EM, BTI and TDDB.
- Strong background in advanced packaging and heterogeneous integration reliability, including TSV-based 2.5D/3D integration, chiplet architectures, and backside power delivery schemes.
- Demonstrated experience translating device- and process-level reliability data into circuit- and system-level reliability metrics for complex digital SoCs and platform-level decision making.
- Drive cross-functional design for reliability collaboration with design, process and reliability teams.
- Proven experience in reviewing and approving design waivers for electromigration (EM) violations in SoC designs, including on-chip metal, bump, and ball interfaces.
- Advanced statistical analysis and lifetime modeling expertise (e.g., Weibull analysis, JMP, Minitab, large-data correlation) used to inform qualification sign-off and risk decisions.
- Recognized technical leadership with a track record of influencing design, process, and program decisions, mentoring engineers, and driving cross-functional alignment across design, product engineering, test, and foundry teams.
- MS or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Physics, or a related field (PhD preferred), with demonstrated industry impact in reliability or technology development.
Pay range and Other Compensation & Benefits: $162,600.00 - $244,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
