We are looking for a Sr. Staff Design Verification Engineer to lead end-to-end verification efforts for our advanced CPU and AI compute platforms. This role is ideal for seasoned engineers with deep expertise in CPU verification who excel at driving complex test plans to closure, mentoring teams, and leveraging modern AI tools to accelerate innovation.
This role is hybrid, based out of Boston, Toronto, Ottawa or Santa Clara.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are- Proven track record leading end-to-end CPU verification across processor cores, caches, interconnects, interrupts, MMU/IOMMU, and cache coherency protocols, with multi-chip and emulation experience a plus.
- Expert in creating comprehensive test plans and building simulation testbenches using SV-UVM, C/DPI, and Cocotb.
- Skilled in managing high-volume regression execution, complex failure triage, and driving test plans and coverage metrics to closure.
- Experienced leader and mentor dedicated to guiding junior engineers and fostering verification best practices across teams.
- Proficient in leveraging modern AI tools like Copilot, Cursor, Claude, Gemini, and ChatGPT to optimize verification workflows.
What We Need- Lead the development and execution of end-to-end DV strategies for CPU and AI accelerator blocks & chiplets, ensuring robust coverage and sign-off.
- Build and maintain advanced simulation environments using SV-UVM, C/DPI, Cocotb, and other methodologies to verify complex designs.
- Drive test plan ownership, including coverage analysis, regression management, triage, and closure for multi-block CPU subsystems.
- Collaborate with design, architecture, post silicon and software teams to review plans and debug issues.
- Mentor junior DV engineers, sharing expertise in verification flows and leveraging AI-assisted tools; support emulation and multi-chip verification flows where applicable, optimizing for scalability and efficiency.
What You Will Learn- How large-scale AI SoCs are architected, integrated, and brought to silicon.
- How verification choices directly impact design performance, power, and overall silicon success.
- How to build and scale DV flows supporting cutting-edge compute architectures.
- How to use AI to increase your productivity
- How to integrate cross-functional workflows across design, DV, physical, and firmware teams.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
