About The RoleEnphase is looking for an experienced Verification Engineer to help validate a custom RISC-V VLIW processor architecture that powers next-generation digital control systems for energy conversion products. You will be responsible for ensuring deterministic and correct operation across the entire compute stack, including custom hardware pipelines, proprietary instruction set extensions, compiler-generated execution schedules, and closed-loop control applications.
This role is ideal for an engineer who thrives at the intersection of processor architecture, hardware verification, compiler technology, and control systems. You will work closely with architecture, RTL, verification, compiler, firmware, and control algorithm engineers to develop comprehensive verification methodologies that ensure safety-critical control loops execute with predictable timing and flawless functional correctness.
As part of this role, you will also contribute to system-level mixed-signal verification environments that combine RTL simulation, real-number modeling, power stage models, and analog simulation platforms to validate real-world control-loop behavior.
What You Will Do - Develop and execute verification strategies for a custom RISC-V VLIW processor architecture and associated instruction set extensions.
- Create and maintain SystemVerilog-based verification environments, assertions, checkers, scoreboards, coverage models, and regression infrastructure.
- Verify pipeline correctness, instruction scheduling behavior, memory subsystem interactions, exception handling, and architectural compliance.
- Develop trace-based validation methodologies to ensure deterministic execution timing for real-time control applications.
- Analyze execution traces, instruction schedules, waveform data, and performance metrics to identify root causes of hardware or compiler issues.
- Collaborate with compiler engineers to validate code generation, instruction scheduling, optimization behavior, and ISA feature utilization.
- Drive hardware/software co-verification efforts spanning RTL, compiler toolchains, firmware, and system-level applications.
- Contribute to mixed-signal verification environments integrating:
- RTL simulation
- SystemVerilog Real Number Modeling (RNM)
- Analog simulation platforms such as NL5
- C/C++ models of power conversion stages and plant models
- Python-based analysis and automation frameworks
- Validate closed-loop control behavior, timing determinism, fault handling, and system-level interactions between digital control algorithms and analog power stages.
- Support verification automation, regression analysis, debug tooling, and continuous improvement of verification methodologies.
- Document verification strategies, debug findings, and architectural insights to support long-term product quality and organizational knowledge sharing.
Who You Are and What You Bring- PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5+ years of relevant industry experience, OR Master's degree with 8+ years of relevant industry experience.
- Strong understanding of processor architecture, pipelined microarchitectures, instruction execution, and computer architecture fundamentals.
- Experience developing verification environments using SystemVerilog and industry-standard verification methodologies.
- Strong debugging and root-cause analysis skills involving complex hardware and software interactions.
- Experience analyzing instruction traces, execution timing, and architectural behavior.
- Proficiency in Python or similar scripting languages for automation, analysis, and verification infrastructure.
- Familiarity with RTL design, simulation, synthesis, and verification workflows.
- Strong written and verbal communication skills with the ability to collaborate across architecture, compiler, firmware, and hardware teams.
- Demonstrated ability to solve technically challenging problems through data-driven analysis and systematic debugging.
Nice to have attributes- Experience with RISC-V processors and ecosystem tools.
- Experience with VLIW architectures, superscalar processors, or instruction scheduling concepts.
- Understanding of compiler internals, code generation, optimization techniques, and scheduling algorithms.
- Experience validating custom instruction set extensions.
- Familiarity with deterministic real-time systems and safety-critical embedded applications.
- Exposure to functional safety standards and methodologies.
- Experience with SystemVerilog Real Number Modeling (RNM) and mixed-signal verification.
- Experience integrating RTL simulation with analog simulators and behavioral system models.
- Knowledge of digital control systems, feedback control theory, power electronics, or power conversion systems.
- Experience implementing C/C++ reference models and architectural golden models.
- Familiarity with coverage-driven verification, formal verification, or constrained-random methodologies.
- Experience building infrastructure for trace analysis, automated triage, and large-scale regression management.
Pay and BenefitsThe base pay range for this position is $135,000 to $205,200. This salary range may be modified in the future. The successful candidate's starting pay will be determined based on relevant skills, experience, education or training, work location, and market conditions. This position is also eligible for generous stock, bonus, and benefits.
