Encore Semi LLC

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract

Encore Semi LLC$150K — $165K *
Technical Services
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • 10+ years of industry experience in ASIC physical design with successful tape-outs on advanced FinFET nodes (14nm/12nm/7nm)
  • Deep expertise in rapid DRC/LVS/ERC closure and final tape-out procedures
  • Hands-on mastery of Synopsys Fusion Compiler (or ICC2) and PrimeTime
  • Strong scripting skills (Tcl, Python, Bash)
  • Preferred: Direct experience with the GlobalFoundries 12LP/12LP+ node and Mentor Calibre

Responsibilities

  • Execute block-level and top-level physical design using the Synopsys Fusion Design Platform (Fusion Compiler)
  • Drive static timing analysis (STA), parasitic extraction, and timing closure across multiple corners using PrimeTime and StarRC
  • Address 12nm FinFET challenges including advanced routing rules, EM/IR-drop analysis, and complex SDC constraint management
  • Perform DRC, LVS, and antenna checks using Calibre and Synopsys IC Validator (ICV)
  • Maintain robust Tcl, Python, or Perl scripts to automate workflows

Benefits

  • 15 days of PTO per calendar year
  • 10 paid Holidays per calendar year
  • 80% of medical premiums covered for Employee and Dependents
  • 50% of dental and vision premiums covered for Employee and Dependents
  • Employee Assistance Program (EAP)
  • 401k - Traditional & Roth options
  • Life Insurance, Long-Term Disability, and AD&D coverage
  • Tuition reimbursement
Full Job Description
Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US Citizen or Lawful Permanent Resident.

We have an immediate need for an expert Physical Design Engineer to drive a high-speed design across the finish line. You will be working on a 1GHz AES hard macro targeted for the GlobalFoundries 12LP (12nm FinFET) process node. The design is nearly complete; your primary objective upon joining will be the final cleanup of 7 remaining DRC/ERC errors, completing fill insertion, and executing the final Calibre signoff checks for tape-out.
Core Technical Environment & Ongoing Responsibilities: Beyond this immediate milestone, you will take ownership of the RTL-to-GDSII flow for our next-generation SoCs, pushing the limits of Power, Performance, and Area (PPA).
  • Implementation: Execute block-level and top-level physical design (floorplanning, CTS, routing) using the Synopsys Fusion Design Platform (Fusion Compiler).
  • Timing & Signoff: Drive STA, parasitic extraction, and timing closure across multiple corners using PrimeTime and StarRC.
  • FinFET Optimization: Address 12nm FinFET challenges including advanced routing rules, EM/IR-drop analysis (Ansys RedHawk), and complex SDC constraint management.
  • Verification: Perform DRC, LVS, and antenna checks using Calibre and Synopsys IC Validator (ICV).
  • Automation: Maintain robust Tcl, Python, or Perl scripts to automate workflows.
Qualifications:
  • 10+ years of industry experience in ASIC physical design with successful tape-outs on advanced FinFET nodes (14nm/12nm/7nm).
  • Deep expertise in rapid DRC/LVS/ERC closure and final tape-out procedures.
  • Hands-on mastery of Synopsys Fusion Compiler (or ICC2) and PrimeTime.
  • Strong scripting skills (Tcl, Python, Bash).
  • Preferred: Direct experience with the GlobalFoundries 12LP/12LP+ node and Mentor Calibre.

The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package.

Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement

LinkedIn :: https://www.linkedin.com/in/rtl2gds/

About Encore Semi LLC

Encore Semi LLC is a semiconductor design and engineering services company that provides custom solutions for complex system-on-chip (SoC) designs. The company was founded in 2013 and is headquartered in San Jose, California. Encore Semi has over 500 employees and serves clients in various industries, including automotive, aerospace, and telecommunications. The company's services include architecture and design, verification and validation, and software and firmware development. Encore Semi is committed to innovation and has received several awards for its services, including the TSMC Open Innovation Platform Partner of the Year Award.
Learn more about Encore Semi LLC
Size
500 employees
Industry
Net Income
$500,000
Founded
2013
5 Year Trend
+30%
Revenue
$50 million

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