Qualifications

• 3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes
• Solid knowledge of the full design cycle from RTL to GDSII and deep submicron design concepts
• Proficient with EDA tools such as Fusion Compiler, Innovus, PrimeTime, Calibre, and Redhawk
• Scripting experience in TCL, Python, or Perl
• Bachelor's degree or higher in Electrical/Electronics, Communication, VLSI, or Microelectronics with strong academic performance

Responsibilities

• Perform physical implementation steps: floor planning, place and route, power/clock distribution, physical verification, and timing closure
• Collaborate with logic designers and the Hardware team to conduct feasibility studies and explore design trade-offs
• Evaluate IP vendors and process nodes, providing technical recommendations
• Develop methodologies and automation scripts for implementation steps from Synthesis to GDSII
• Conduct static timing analysis, create timing constraints, validate critical paths, and ensure timing closure
• Manage physical verification and IR/EM analysis on blocks and full chips

Benefits

• Flexible and hybrid working schemes
• Minimum of 90 days of Maternity and Paternity Leave with a return option within a year
• Life insurance for all employees
• Well-being programs for mental and physical health support
• Opportunities to join Employee Resource Groups (NERGs)
• Personalized career and skills development support through Employee Growth Solutions
• Access to a diverse pool of Coaches and Mentors
• Learning environment that fosters personal and professional growth