Full Job Description
The Role and Impact
Join Intel's distinguished team as an SoC Logic Design Engineer. In this role, you will pioneer the development of cutting-edge System-on-Chip (SoC) solutions, contributing to Intel's mission of creating transformative technology that drives global innovation. As a key member of our team, you will have the opportunity to influence the architecture, design, and integration of next-generation SoCs. Your contributions will directly impact Intel's ability to deliver world-class products with optimal performance, power efficiency, and scalability, shaping the future of the semiconductor industry.
Key Responsibilities
- Develop high-quality logic designs, including Register Transfer Level (RTL) coding and simulations, for innovative SoCs.
- Collaborate with architects to define and implement microarchitecture features of SoC blocks.
- Integrate and validate Intellectual Property (IP) blocks and subsystems into full-chip SoC designs.
- Perform quality checks and optimize designs to meet power, performance, area, and timing objectives, ensuring seamless production readiness.
- Review verification plans to confirm design features are thoroughly verified and address any RTL test failures with corrective measures.
- Employ secure development practices to mitigate security risks and maintain design integrity.
- Work with IP providers to integrate and validate IPs at the SoC level.
- Drive quality assurance compliance to enable efficient IP-SoC handoffs.
Qualifications:
Minimum Qualifications
To excel in this role, you must meet the following requirements:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 4+ years of relevant experience
- OR Master's degree in Electrical Engineering, Computer Engineering, or a related field and 3+ years of relevant experience
- OR PhD in Electrical Engineering, Computer Engineering, or a related field and 6+ months of experience.
Experience must be in:
- Expertise in RTL development, System Verilog, and SoC logic integration.
- Proficiency in microarchitecture definition, logic design, and simulation.
- Strong understanding of SoC design methodologies, including timing/power convergence and physical implementation.
Preferred Qualifications
Candidates with the following qualifications will have an advantage:
- Hands-on experience with Python, Perl, or other scripting languages.
- Familiarity with advanced Front-End RTL Design tools such as Lint, CDC, Synthesis, and Static Timing Analysis (STA).
- Experience in validation development, pre-silicon testing, and DFT/DFD tools.
- Knowledge of industry-standard IPs, fabrics, and UVM-based verification.
We are looking for innovators passionate about advancing technology. Embark on a career journey where your work will leave a profound impact on the future of computing. Apply now and help Intel create world-changing technology.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara, US, Texas, Austin
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
