General Summary:Qualcomm's validation team is part of the central Global SoC digital hardware organization responsible for the overall quality of the SoC silicon. The validation team works closely with architects, designers, verification engineers, software engineers, and customers. The team is currently seeking candidate specifically for SOC Infrastructure/NoC, Power and Performance Validation in pre-silicon emulation and post-silicon.
The candidate is expected to have an excellent understanding of digital design fundamentals, on-chip interconnects, writing content to validate and analyze SOC bus architecture ,performance and power.
Required Skills:- SOC Bandwidth, QoS, Latency and Throughput analysis
- Interconnect architectures - NoCs,AXI, AHB etc. Knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverage
- Solid expertise in various FIFO designs and related performance/functionality aspects
- Come up with thorough performance validation plans and work closely with team members to ensure Performance-Power trade-offs are factored in
- System Low power modes
- Dynamic clock and voltage scaling operations
- Interrupt architecture
- Debug architecture - interactions with JTAG based debuggers, state dump scripts
- Performance monitor architecture
- Thorough understanding of CPU and DDR concepts, Mumtimedia, GPU, Peripheral,
- Memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, MTE, MPAM
- Experience in embedded systems/expertise in C, C++, Python and assembly languages
- Design and Implementation of drivers and test content
- Debugging low level software and hardware issues
- Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design
- Familiarity in debug tools including JTAG and kernel debuggers
- Structured program development concepts
- Logical thinking and problem-solving ability with focus on Power, Performance and SoC System feature validation
- Experience leveraging Generative AI technologies for optimizing workflows
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 5+ years of ASIC Design, Validation, Verification, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 4+ years of ASIC Design, Validation, Verification, or related work experience.
OR
PhD in Science, Engineering, or related field and 3+ years of ASIC Design, Validation, Verification, or related work experience.
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Pay range and Other Compensation & Benefits: $121,800.00 - $182,600.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
