Serdes Characterization & Post-Silicon Validation Engineer

K2 Space

$170K — $250K *
Telecommunications & Hardware
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in high-speed SerDes characterization, post-silicon validation, or signal integrity.
  • Strong knowledge of NRZ/PAM4 signaling, equalization, and related fundamentals.
  • Hands-on proficiency with high-bandwidth oscilloscopes, BERTs, and other high-speed measurement tools.
  • Expertise in eye diagrams, jitter decomposition, and BER testing techniques.
  • Familiarity with package/PCB channel dynamics and related signal integrity issues.
  • Experience in automating test environments using Python or similar languages.

Responsibilities

  • Lead characterization of high-speed NRZ and PAM4 SerDes interfaces.
  • Develop electrical characterization plans under various conditions.
  • Assess TX/RX performance metrics like eye quality and link margin.
  • Validate equalization techniques and debug complex link issues.
  • Conduct BER and stress testing across varying channels.
  • Correlate silicon measurements with models and simulations.
  • Partner with cross-functional teams for system-level link validations.
  • Contribute to building the validation lab and automation infrastructure.

Benefits

  • Comprehensive benefits package including medical/dental/vision coverage.
  • Paid time off and life insurance.
  • Paid parental leave available.
  • Company equity opportunities.
  • Numerous additional perks.
Full Job Description
About the Role
We are looking for a hands-on SerDes Characterization & Post-Silicon Validation Engineer to bring up, characterize, and validate high-speed SerDes interfaces in complex SoCs.

You will work closely with SerDes/IP, mixed-signal, digital, firmware, SI/PI, package, board, and systems teams to take high-speed interfaces from first silicon through product integration and system-level operation. You will also help build our high-speed test and validation capability from the ground up.

Responsibilities
  • Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes, including 112G-class interfaces.
  • Develop and execute electrical characterization plans across lanes, data rates, voltage, temperature, channels, and operating conditions.
  • Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, bathtub curves, CDR performance, and link margin.
  • Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link-training behavior.
  • Perform BER and stress testing across representative and worst-case channels.
  • Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic.
  • Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis.
  • Partner with firmware and digital teams on SerDes configuration, initialization, diagnostics, adaptation, and system-level link bring-up.
  • Develop automated characterization and regression environments for instrument control, data collection, analysis, and reporting.
  • Support the transition from chip-level SerDes characterization to product integration and system-level validation.
  • Contribute to building the high-speed validation lab, equipment, test infrastructure, measurement methodology, and automation from the ground up.

Qualifications
  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience.
  • Strong understanding of high-speed serial-link fundamentals, including NRZ/PAM4 signaling, equalization, CDR, jitter, BER, channel loss, and link budgets.
  • Deep hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment.
  • Experience with eye diagrams, jitter decomposition, bathtub curves, BER testing, stressed-eye testing, and receiver sensitivity characterization.
  • Strong understanding of package/PCB channels, insertion/return loss, crosstalk, reflections, and channel de-embedding.
  • Experience developing automated characterization environments using Python or similar scripting languages and instrument-control interfaces.
  • Strong debugging skills across silicon, package, PCB, firmware, and system boundaries.
  • Ability to work closely with SerDes IP/design, SI, package, board, firmware, and digital teams.

Preferred Qualifications
  • Experience with 112G+ PAM4 SerDes characterization and validation.
  • Experience with Ethernet, PCIe, JESD204, Interlaken, or chip-to-chip interfaces.
  • Experience with compliance testing and high-speed interface standards.
  • Familiarity with SerDes behavioral/channel models and simulation-to-measurement correlation.
  • Experience with SerDes IP integration and validation from third-party IP vendors.
  • Experience with advanced package and high-loss PCB channels.
  • Familiarity with high-speed clocking, PLLs, reference-clock jitter, and power-supply noise effects on SerDes performance.
  • Experience with automated PVT characterization and large-scale measurement data analysis.

Compensation and Benefits:
  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks


If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

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