Senior Yield Enhancement Engineer #9573

Taiwan Semiconductor Manufacturing Company Limited

$100K — $130K *
Manufacturing & Automotive
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Master's degree in Electrical Engineering, Material Science, Physics, or related field required with 2 years of relevant experience.
  • 1 year of experience with defect inspection metrologies like Bright Field (BF), Dark Field (DF), or Electron Beam Inspection (EBI).
  • 1 year of experience in defect review metrologies such as Scanning Electron Microscopy (SEM), Critical Dimension SEM (CD-SEM), or Transmission Electron Microscopy (TEM).
  • Experience working in an ISO 4 (Class 10) cleanroom environment is essential.
  • Familiarity with semiconductor physics, CMOS device operation, or advanced semiconductor manufacturing required.
  • Hands-on experience with at least 2 semiconductor processes like LIT, ETC, CVD, PVD, DIF, and CMP.

Responsibilities

  • Define a defect reduction roadmap and collaborate with various departments for process optimization.
  • Own metrology tools and recipes, optimizing inline inspection for defect detection.
  • Monitor and detect tool shifts in a high-volume semiconductor manufacturing environment.
  • Resolve process issues and ensure adherence to escalation procedures.
  • Guide production lines using statistical process control to maintain production health.
  • Eliminate process defects in collaboration with process engineers and design experiments to support findings.
  • Coordinate yield improvement, defect reduction, and quality enhancement projects.

Benefits

  • Comprehensive medical, dental, and vision plan options available.
  • Income-protection programs for injury or illness.
  • 401(k)-retirement savings plan to secure financial future.
  • Competitive paid time-off and holidays to recharge.
  • Focus on overall health and well-being, enhancing physical, mental, and financial health.
Full Job Description
Company

TSMC Arizona Corporation

Location

USA-Arizona

Posted

Mar 16, 2026

Senior Yield Enhancement Engineer #9573

Senior Yield Enhancement Engineer - Brief Description
Work independently with cross-departmental teams to transfer advanced semiconductor technology (below N4 technology) from Taiwan to overseas fabs, ensuring a successful ramp-up. Responsible for product yield improvement and meeting all customer requirements.

Responsibilities:
  • Define an aggressive defect reduction roadmap, identify potential yield-limiting defect sources, and collaborate with all internal departments, including integration, process engineering, and manufacturing, to optimize manufacturing processes.
  • Become the metrology tool and recipe owner, setting up and optimizing inline inspection and review recipes to enhance the capability for inline defect detection.
  • Utilize these tools to monitor and detect integrated and process tool shifts in a high-volume advanced semiconductor manufacturing fab.
  • Resolve issues and ensure proper escalation processes are followed.
  • Provide production line guidance and utilize statistical process control principles to sustain production line health and prevent defect-induced excursion events.
  • Coordinate with process engineers to identify and eliminate process and station defect sources, design and execute experiments, and interpret and extract insightful results from complex data sets to implement solutions promptly.
  • Serve as the project owner to coordinate overall yield improvement, defect reduction, quality enhancement, and new process technology qualification.

Minimum Qualifications/Requirements:

Education and Work Experience:
  • Master's degree (or foreign equivalent) in Electrical Engineering, Material Science, Physics, or a related field plus 2 years of experience in a process, equipment or integration semiconductor engineering role.

Technical Skills:
  • Must have 1 year of experience studying recipes in at least one of the following defect inspection metrologies used in the semiconductor industry: Bright Field (BF) inspection tool, Dark Field (DF) inspection tool, or Electron Beam Inspection (EBI) tool.
  • Must have 1 year of experience in at least one of the following defect review metrologies used in the semiconductor industry: Scanning Electron Microscopy (SEM), Critical Dimension SEM (CD-SEM), or Transmission Electron Microscopy (TEM).
  • Must have experience working in an ISO 4 (Class 10) or lower cleanroom environment.
  • Must have experience in at least 1 of the following: semiconductor physics, CMOS device operation, or advanced semiconductor manufacturing.
  • Must have experience with 2 of the following processes, including relative tool structure and process mechanism: LIT, ETC, WET, CVD, PVD, DIF, and CMP.

Physical Requirements:
  • Candidates must be willing and able to work on-site at our Phoenix Arizona facility.

Standard Work Hours: 40 hrs/week, Mon-Fri, 8:30 a.m. - 5:30 p.m.

As a valued member of the TSMC family, we place a significant focus on your health and well-being. When you are at your best-physically, mentally, and financially-our company is at its best. We offer a comprehensive and competitive benefits program that provides the resources you need to help you manage your health and achieve your goals across many areas of your life. This includes a variety of medical, dental, and vision plan offerings you can choose from that best fit you and your family's needs. Additionally, TSMC provides income-protection programs to financially assist you should you experience an injury or illness, and a 401(k)-retirement savings plan to help you secure your financial future. TSMC also offers competitive paid time-off programs and paid holidays allowing you to recharge and spend time with your family and loved ones.

Work Location:
5088 W. Innovation Circle, Phoenix, AZ 85083

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