SiFive

Senior Staff RTL Design Engineer - CPU Frontend

SiFive$205K — $251K *
Telecommunications & Hardware
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • BS/MS in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
  • 7+ years of design experience in CPU RTL design.
  • Experience with instruction fetch, decode, branch prediction, coherent caches, etc.
  • Proficient in Verilog, System Verilog, or VHDL for hardware (RTL) design.
  • Strong software engineering background, with skills in functional programming, templated metaprogramming, and compiler infrastructures.
  • Attention to detail and focus on high-quality design.
  • Ability to collaborate effectively in a team environment.

Responsibilities

  • Architect and implement features and enhancements in RISC-V CPU cores using Chisel.
  • Integrate designs into SiFive's Chisel/FIRRTL framework and improve automated generation processes.
  • Conduct initial sandbox verification and collaborate on thorough verification test plans.
  • Work with the physical implementation team to optimize designs for performance and power.
  • Collaborate with performance modeling team for optimization to meet performance goals.
  • Develop microarchitecture specifications and maintain thorough documentation.

Benefits

  • Eligible for healthcare and retirement plans.
  • Paid time off.
  • Variable/incentive compensation or equity options.
Full Job Description

Job Description:

The Role

As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

  • Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.

  • Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.

  • Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.

  • Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.

  • Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.

  • Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Requirements

  • BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.

  • 7+ years of design experience.

  • Academic or professional experience with CPU RTL design in one or more of the following areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.

  • Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.

  • Strong software engineering skills/background, including:

    • Object-oriented, aspect-oriented, and particularly functional programming

    • Templated metaprogramming, in any language

    • Compiler infrastructures, particularly for domain-specific languages

    • Data modeling, particularly intermediate representations for optimizing or transforming compiler passes

    • Test-driven development, particularly ability to write adaptive unit tests

  • Attention to detail and a focus on high-quality design.

  • Ability to work well with others and share the belief that engineering is teamwork.

Nice-to-haves

  • Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.

  • Knowledge of RISC-V architecture.

  • Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch; instruction decode; register renaming and instruction scheduling; vector units; load-store unit.

  • Knowledge of verification principles, testbenches, UVM, and coverage.

  • Experience with Git/Github, Jira, Confluence.

Pay & Benefits

Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

$205,740.00-$251,460.00

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in

United States of America

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

About SiFive

SiFive is a semiconductor company that designs and develops custom chips based on the RISC-V instruction set architecture. The company was founded in 2015 by a team of experts in computer architecture and chip design and is headquartered in San Mateo, California. SiFive's mission is to democratize access to custom silicon and enable innovation for all. The company has raised over $190 million in funding to date and has partnerships with several leading technology companies.
Learn more about SiFive
Size
300 employees
Industry
Founded
2015

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