Position Summary: We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next generation SOCs. This is a highly visible hands-on role leading individual and team contributions to Fabric, System cache and DRAM controller sub-system architecture, interface, performance and power tradeoffs.
Position Responsibilities:- Guide on development of innovative Fabric, System cache and DRAM controller Architectural and microarchitectural features to boost power and performance on various targeted workloads in next generation SOCs
- Identify and deliver Fabric, System cache and DRAM controller subsystem architecture proposals for products in new and existing markets
- Evaluate architecture proposal benefits in collaboration with team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership)
- Perform high-level performance modeling/simulation and analysis of Fabric, System cache and DRAM controller features, applications, benchmarks, and complex uses cases
- Direct and orchestrate performance modeling, and studies to support inclusion of these features in the next generation "Fabric, System cache and DRAM controller" microarchitecture based on performance, area or power improvement
- Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership
- Collaborate with silicon bring-up and product teams to verify and debug the proposal and its delivered performance
- Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentations
Required Skills:- BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
- 12+ years of experience in SOC or ASIC design and architecture
- Prior direct experience (> 9 years) in Fabric, System Cache, DRAM controller Architecture or microarchitecture is required
- Understanding of memory controller architecture, memory scheduling, prioritization and QoS
- Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB)
- Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
- Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area
Special Attributes:- Experience with BookSim Simulator
- Experience with Platform Architect
Our total rewards programs are designed to motivate and engage exceptional talent. The hourly pay rate range for roles at this level is listed below, but may be higher or lower in other states due to geographic differentials in the labor market. Within the hourly pay rate range, individual rates depend on a number of factors-including the role's function and location as well as the individual's knowledge, skills, experience, education and training. This is part of our comprehensive compensation package with annual bonus eligibility and generous benefits to help you live life well.
Hourly Pay Rate Range
$197,800-$296,600 USD
Additional Information Disclosure of Trade Secrets
Samsung has a strict policy on trade secrets. In applying to Samsung and progressing through the recruitment process, you must not disclose any trade secrets of a current or previous employer.
Essential Job Functions
This position will be performed in an office setting. The position will require the incumbent to sit and stand at a desk, communicate in person and by telephone, and frequently operate standard office equipment, such as telephones and computers.
