We are seeking an innovative Senior STA Signoff Methodology Engineer to help drive sign-off strategies for the world's leading GPUs, CPUs, LPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, insightful analysis, and automation. This work will influence the entire next generation AI landscape through critical contributions across NVIDIA's many product lines. We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 3nm and beyond, this is an ideal role. What you'll be doing: • Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing. • Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electro migration, and other advanced-node physical effects. • Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy sophisticated timing-signoff strategies for extraordinary silicon performance. • Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond the capabilities of standard EDA tools. • Work across STA, constraints, and timing and power optimization. • Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation. What we need to see: • MS in Electrical or Computer Engineering, or equivalent experience, with 8 years of experience in ASIC design and timing. • Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations. • Proven foundation in the mathematics and physics underlying electrical design. • Experience with low-power techniques, including multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC. • Understanding of signal and power integrity, crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop. • Understanding of standard-cell, memory, and I/O IP modeling and their use in ASIC flows. • Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond. • Familiarity with industry-standard ASIC tools such as PrimeTime, ICC2, RedHawk, and Tempus. • Strong communication skills and a collaborative working style. Ways to stand out from the crowd: • Familiarity with 3D IC integration, die stacking and packaging, self-heating, and their impact on timing closure. • Strong data-analysis and modeling skills employing Python, JMP, or similar platforms. • Proficiency in Tcl and Python; C++ experience is a plus. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and . Applications for this job will be accepted at least until August 24, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.