Teradyne

Senior RTL Digital Design Engineer (TERADYNE, North Reading, MA)

Teradyne$192K — $307K *
Consumer Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • BSEE required; MSEE or PhD preferred.
  • 8+ years of experience in ASIC or digital design.
  • Expertise in Verilog/SystemVerilog RTL development.
  • Experience designing complex digital blocks like state machines and FIFOs.
  • Knowledge of ASIC development flows including synthesis and timing analysis.
  • Experience with third-party and custom IP integration.
  • Scripting proficiency in Python, Tcl, or similar languages.

Responsibilities

  • Drive digital design from architecture definition to silicon bring-up.
  • Collaborate with architects, analog designers, and verification engineers.
  • Own critical ASIC subsystems and influence technical direction.
  • Contribute to the design of next-generation semiconductor test systems.
  • Support verification, silicon bring-up, and debugging activities.

Benefits

  • Comprehensive health programs including medical, dental, and vision.
  • Flexible Spending Accounts and retirement savings plans.
  • Life and disability insurance coverage.
  • Paid vacation and holidays.
  • Tuition assistance programs.
Full Job Description
Opportunity Overview

Teradyne's Digital ASIC Group is seeking a Senior RTL Digital Design Engineer to help develop complex mixed-signal ASICs for next-generation semiconductor test systems. Working closely with architects, analog designers, verification engineers, and physical design teams, you will drive digital design activities from architecture definition through silicon bring-up. This role offers the opportunity to own critical ASIC subsystems, influence technical direction, and contribute to cutting-edge products in a highly collaborative environment.

Required Qualifications
  • BSEE required; MSEE or PhD desired.
  • 8+ years of ASIC or digital design experience with strong expertise in Verilog/SystemVerilog RTL development.
  • Proven experience designing complex digital blocks including state machines, FIFOs, high-speed datapaths, arbitration logic, and DFT-friendly architectures.
  • Strong knowledge of ASIC development flows including synthesis, static timing analysis (STA), clock domain crossing (CDC), and timing closure.
  • Experience integrating third-party and custom IP into large-scale SoCs or mixed-signal ASICs.
  • Proficiency with scripting and automation using Python, Tcl, Make, or similar languages.
  • Experience supporting verification, silicon bring-up, debugging, and root-cause analysis.
  • Strong collaboration, communication, and problem-solving skills with the ability to mentor junior engineers and drive technical excellence across cross-functional teams.


Compensation: The base salary range for this role is $192,300 - $307,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of comprehensive health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

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About Teradyne

Teradyne, Inc. is a leading supplier of automation equipment for test and industrial applications. Teradyne Automatic Test Equipment (ATE) is used to test semiconductors, wireless products, data storage and complex electronic systems, which serve consumer, communications, industrial and government customers. Industrial Automation products include Collaborative Robots used by global manufacturing and light industrial customers to improve quality and increase manufacturing efficiency. In 2019, Teradyne had revenue of $2.3 billion and today employs 5,500 people worldwide. For more information, visit teradyne.com. Teradyne(R) is a registered trademark of Teradyne, Inc. in the U.S. and other countries.
Learn more about Teradyne
Size
5,900 employees
Market Cap
$13.1 billion
Industry
Net Income
$784.1 million
Founded
1960
5 Year Trend
+16.1%
Revenue
$3.1 billion
NASDAQ

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