What you'll do:As a Senior Power Delivery Architect, you will be responsible for designing the complete power delivery system for Persimmons' AI accelerator - a grid of hundreds of chiplets drawing thousands of amps from a 48V datacenter rack and delivering clean, stable power to silicon cores operating at sub-1V. This is not a standard board power project. Your primary duties and responsibilities include:
- Architect the rack-to-silicon power delivery network, designing the complete roadmap from 48V datacenter busbar power down to sub-1V silicon cores across a multi-chiplet grid at hyperscale.
- Own regulator integration strategy - evaluating and deploying high-frequency, multi-phase VRMs, Co-packaged Voltage Regulators (CPVR), and Vertical Power Delivery (VPD) architectures to meet the power density and efficiency demands of our chiplet grid.
- Design the multi-tier decoupling capacitor hierarchy - bulk, PCB, package, and on-chip/deep trench - running simulations to maintain stable target impedance across the full delivery stack.
- Model and mitigate extreme di/dt transient events and IR drop across the 400-chiplet grid, eliminating dynamic voltage droop that would otherwise compromise silicon reliability and performance.
- Partner cross-functionally with silicon, advanced packaging (2.5D/3D interposers), and thermal teams to run full-system electro-thermal and electromagnetic co-simulations, ensuring power delivery co-design is baked in from day one.
- You will use AI to attack the highest-cost parts of power delivery. IR drop analysis, electromigration debugging, power grid optimization, signoff iteration. Wherever the work is repeatable, you will replace manual effort with intelligent agents and structured automation.
RequirementsWhat You Bring To The Table:- Educational Foundation: Bachelor's or Master's degree in Electrical Engineering, Power Electronics, or a related technical field. A PhD with focus on power delivery, electromagnetics, or advanced packaging is a strong plus.
- Proven Experience: 8+ years of hands-on power delivery experience spanning chip-level PDN, package-level power delivery, and system/rack-level power architecture - ideally on high-density compute or AI accelerator platforms.
- Specialized Expertise: Deep knowledge of rack-to-silicon PDN design including 48V busbar architectures, VRM/CPVR/VPD technologies, multi-tier decoupling strategy, and transient current management at scale. Experience with 2.5D/3D advanced packaging constraints and their impact on power delivery is highly valued.
- Technical Mastery: Proficiency with power delivery simulation and analysis tools - including EMIR, electrothermal, and electromagnetic co-simulation - alongside strong fundamentals in power electronics and high-current system design.
- Collaborative Track Record: Proven ability to drive cross-domain co-design across silicon, packaging, thermal, and system teams, owning power delivery architecture from rack to die and delivering production-ready solutions on schedule.
Benefits- Competitive salary and benefits package
- Flexible PTO
- 401k
