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X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications: - Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8 years of physical design experience
- Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
- Experience in high performance synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.
Preferred qualifications: - Experience in top-level floorplanning, block integration.
- Experience in low power design Implementation including UPF/CPF, multi-voltage domains, power gating.
- Experience with ASIC design flows and methodology of Physical design.
- Knowledge of fundamentals of computer architecture and of Verilog/SystemVerilog.
- Understanding of Circuit design, device physics and deep submicron technology.
- Exceptional skills with scripting languages such as Tcl, or Perl.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Develop all aspects of ASIC Register Transfer Level to Graphic Data System (RTL2GDS) implementation for high Power, Performance, and Area (PPA) designs.
- Manage full-chip level physical implementation.
- Define and implement innovative schemes to improve Performance and Power.
- Work with cross functional teams to deliver best Quality of results.
