This is a senior layout design manager position. In this role you and your team will lead design enablement of advanced high-speed analog circuits in the latest deep-submicron CMOS and/or BiCMOS technologies. You9ll drive and implement best-in-class high-speed analog layouts that extract the highest performance from the world9s most advanced CMOS and BiCMOS technologies. These analog macros include electrical interface-facing DAC and ADC based SERDES solutions for 112G and 224G, optical-line-facing high-speed DAC and ADC circuits working with optical modulators and detectors, transimpedance amplifiers, modulator driver circuits, and critical precision analog circuits for control and monitoring functions.
How Will You Contribute - Work closely with Ciena9s international layout, circuit design, and packaging groups across different time zones and regions.
- Plan and schedule projects to ensure successful delivery while maintaining a healthy work-life balance for the team.
- Lead Block and Macro level layout development including floor-planning, layout creation and optimization.
- Perform feasibility work with various circuit topologies working with senior analog designers to achieve a best-in-class solutions to carry through detailed implementation by weighing tradeoffs and discussing these with other members of the team.
- Undertake physical verification and electromigration checks
- Perform PERC verification and debugging for ESD structures.
- Automate layout flows with scripts and pcells.
- Develop and implement template-based layout methodology.
- Provide status updates on a regular basis, participate in team meetings and share experience with the broader team.
- Mentor junior team members and co-op students
Must Haves - 15+ years of layout experience
- Bachelor9s degree in electrical or computer engineering, computer science, or in a related field.
- Proven experience in leading analog high-speed layout design within advanced BiCMOS and/or CMOS technologies, with years of industry experience.
- Successful experience in managing and delivering MPWs, test chips, and product chips.
- Ability to thoroughly understand challenging design rules from leading-edge manufacturing processes.
- Proficient in reading and debugging Calibre/ICV verification decks.
- Highly motivated self-starter with the ability to work independently while also contributing effectively as part of a team.
- Demonstrated ability to methodically solve complex technical challenges.
- Strong organizational, written, and verbal communication skills.
- Advanced proficiency with industry-standard analog design tools such as Cadence, Mentor, and Synopsys (e.g., Virtuoso, Calibre).
Pay Range: $171,200 - $273,400 CAD
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
