General Summary:Qualcomm Central Hardware Systems (CHS) team is seeking a
Senior Leader, Electrical & Optical Systems Engineer to define, develop, and productize next-generation electrical and optical interconnect technologies for AI, hyperscale datacenter, networking, and HPC systems.
The successful candidate will be a recognized technical leader with deep expertise in
224G/448G SerDes, electrical-optical system co-design, SI/PI, DSP algorithms, EIC/PIC integration, optical networking, advanced packaging, and end-to-end system architecture. This role spans silicon, photonics, packaging, PCB, flyover interconnects, optics, and rack-scale infrastructure.
Impact:Serve as a senior technical leader driving Qualcomm's transition from conventional PCB-based interconnects to
NPC/CPC flyover architectures, co-packaged optics, silicon photonics, and EIC/PIC-integrated systems, enabling scalable AI infrastructure beyond 224G and toward 448G-per-lane technologies.
Key Responsibilities:- Define and drive end-to-end architecture for next-generation interconnect solutions utilizing 112G, 224G, and emerging 448G SerDes technologies, Co-Packaged Optics (CPO), Near-Packaged Optics (NPO), Linear Pluggable Optics (LPO), Co-Packaged Connectors (CPC), Near-Package Connectors (NPC), copper and optical flyover architectures, Active Electrical Cables (AEC), and advanced optical interconnects.
- Lead system design and performance closure across SerDes and PHY architectures, EIC/PIC integration, optical engines, transceiver subsystems, advanced package substrates, PCB channels, connectors, cables, optics, power delivery, thermal, and mechanical architectures.
- Own SI/PI methodology and end-to-end link analysis including channel budgeting, COM analysis, jitter, crosstalk, insertion loss, return loss, equalization strategy, and simulation-to-silicon correlation.
- Drive electrical-optical DSP architecture and algorithm development including TX/RX equalization, CDR, adaptive filtering, FEC, impairment compensation, channel optimization, and overall system performance analysis.
- Develop system-level models and architecture tradeoff studies spanning bandwidth, reach, power, latency, reliability, manufacturability, cost, and scalability.
- Provide technical leadership across silicon, package, optics, platform, and software organizations while driving technology roadmaps and productization from concept through deployment.
Qualifications:- Demonstrated success productizing 112G and/or 224G PAM4 electrical and optical communication systems.
Technical Expertise:Deep expertise in:
- High-speed SerDes architectures
- Electrical-optical DSP algorithms
- PAM4 communication systems
- Signal Integrity (SI) and Power Integrity (PI)
- EIC/PIC co-design and heterogeneous integration
- Optical transceivers and optical engines
- Co-packaged and near-packaged optics
- Advanced packaging, PCB, connector, cable, CPC, NPC, and flyover technologies
- End-to-end system modeling and architecture
- AI networking, scale-up, and scale-out infrastructures
- Hands-on experience with: ADS, HFSS, CST, HSPICE, MATLAB, Python, Cadence Sigrity, Lumerical, Zemax, Verilog-A, SystemVerilog, COM analysis tools, IBIS-AMI modeling
Preferred Qualifications- MS or PhD in Electrical Engineering, Optical Engineering, Physics, or a related discipline.
- 15+ years of experience developing high-speed communication, networking, or optical interconnect products.
- Experience developing and productizing 224G+ electrical and optical interconnect solutions.
- Experience with CPO, NPO, CPC, NPC, flyover copper, flyover optical, silicon photonics, and EIC/PIC integration.
- Familiarity with Ethernet, PCIe, UALink, NVLink, OIF CEI, IEEE 802.3, and emerging AI interconnect standards.
- Experience with chiplets, UCIe, silicon photonics, 2.5D/3D integration, and advanced packaging technologies.
- Track record influencing industry standards, technology roadmaps, and large cross-functional architecture decisions.
- Proven success leading and mentoring senior technical teams across multiple engineering disciplines.
Minimum Qualifications:• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 10+ years of System/Package Design/Technology Engineering or related work experience.
OR
Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 9+ years of System/Package Design/Technology Engineering or related work experience.
OR
PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 8+ year of System/Package Design/Technology Engineering or related work experience.
Pay range and Other Compensation & Benefits: $249,900.00 - $374,900.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
