MS/PhD in Materials Science, Electrical Engineering, Chemical Engineering, Mechanical Engineering or related field
5+ years of hands-on experience in semiconductor packaging or wafer fab process engineering with OSATs
Direct experience with TSV reveal and C4 bumping processes
Strong understanding of 2.5D/3D packaging architectures
Deep knowledge of semiconductor device physics and packaging materials
Experience with statistical process control and yield analysis
Familiarity with metrology tools relevant to bumping/TSV
Excellent cross-functional communication skills.
Responsibilities
Lead architecture and design of advanced semiconductor packaging solutions
Develop and optimize TSV reveal processes
Own C4 bumping process flows for flip-chip applications
Create and maintain process control plans and yield improvement roadmaps
Partner with engineering teams to optimize integration processes
Troubleshoot process excursions using FA data and metrology
Support new product/technology introduction from pathfinding to HVM transfer
Mentor junior engineers and contribute to process documentation.
Benefits
Comprehensive health benefits
401(k) plans with company match
Generous paid time off
Professional development opportunities
Flexible work arrangements.
Full Job Description
About the role:
Lead the architecture, design, and development of advanced semiconductor packaging solutions, including 2.5D/3D IC, System-in-Package (SiP), Flip Chip, and Wafer-Level Packaging
Lead development, characterization, and optimization of TSV (Through-Silicon Via) reveal processes, including back grind, CMP, dielectric/barrier reveal etch, and thickness/uniformity control across wafer thinning stacks
Own C4 bumping process flows - UBM deposition, solder bump plating or ball drop, reflow, and flux clean - for flip-chip and 3D-IC applications
Develop and maintain process control plans (SPC), DOEs, and yield improvement roadmaps for optical engine packaging and bumping modules
Partner with integration engineering to co-optimize TSV reveal with downstream hybrid bonding, micro-bump, or RDL processes
Troubleshoot excursions using FA data, cross-sections, and metrology (CD-SEM, profilometry, XRF, AOI) to root-cause defects such as TSV protrusion variation, via reveal non-uniformity, bump voiding, or co-planarity issues
Support new product/technology introduction (NPI) from pathfinding through HVM transfer
Collaborate cross-functionally with design, reliability, and test teams to ensure package-level electrical and mechanical performance targets are met
Mentor junior engineers and contribute to internal process documentation and best-practice standards
Qualifications:
MS/PhD in Materials Science, Electrical Engineering, Chemical Engineering, Mechanical Engineering or related field
5+ years of hands-on experience in semiconductor packaging or wafer fab process engineering - working with major OSAT's (ASE, AMKOR, SpiL etc). An extensive personal network within key OSATs would be very advantageous
Direct, hands-on experience with TSV reveal (grinding, CMP, dielectric reveal, thickness metrology) and C4 bumping (UBM, electroplating or solder ball attach, reflow)
Strong understanding of 2.5D/3D packaging architectures (interposers, chiplets, HBM integration, hybrid bonding is a plus)
Deep understanding of semiconductor device physics, packaging materials, and thermal/mechanical analysis
Experience with statistical process control, DOE methodology, and yield analysis
Familiarity with metrology and inspection tools relevant to bumping/TSV (CD-SEM, AFM, profilometers, X-ray, AOI/SEM defect review)
Working knowledge of cleanroom fab operations and contamination control
Excellent cross-functional communication skills; comfortable working with equipment OEMs and multi-site teams
Preferred Qualifications:
Experience with copper pillar bumping, micro-bump, or hybrid bonding processes
Background in wafer thinning and temporary bonding/debonding for advanced node packaging
Exposure to reliability testing (thermal cycling, electromigration, HAST) for packaged parts
Experience supporting HVM ramp in an OSAT or IDM environment
