Senior IC Layout Designer (Remote - USA)Employment Type: Full-Time (Hourly) | Contractor Opportunities Available
Compensation: Competitive Hourly Rate + Benefits + Bonus Opportunities
Work Authorization: US Citizen or Lawful Permanent Resident
Location: 100% Remote (Anywhere in the USA)
We are looking for a
Senior IC Layout Designer to join a highly skilled semiconductor engineering team developing advanced
digital and mixed-signal integrated circuits. This role is ideal for an experienced layout professional who enjoys solving complex physical design challenges and turning innovative circuit designs into
high-quality, production-ready silicon.
You will work closely with
IC designers, verification engineers, and process teams to deliver layouts optimized for
performance, power, area, reliability, and manufacturability across advanced process technologies.
What You'll Do- Develop block-level and full-chip physical layouts for complex digital and mixed-signal IC designs.
- Translate schematics into high-quality layout implementations while maintaining design intent.
- Perform floorplanning, placement, routing, optimization, and layout refinement for PPA (Power, Performance, Area).
- Drive DRC, LVS, and ERC closure, including debugging complex layout and verification issues.
- Analyze and optimize layouts for parasitics, signal integrity, timing, and manufacturability.
- Collaborate with circuit designers, physical verification teams, and foundry partners during tapeout and silicon release activities.
- Support improvements in layout methodologies, automation, and design flows.
- Mentor junior layout engineers and contribute technical expertise across the team.
What You Bring- 7+ years of hands-on IC layout design experience in advanced semiconductor technologies.
- Strong expertise with industry-standard EDA tools such as Cadence Virtuoso, Synopsys tools, or equivalent platforms.
- Deep understanding of CMOS process technology, physical design concepts, and layout best practices.
- Proven experience achieving DRC/LVS closure and resolving complex physical verification challenges.
- Strong knowledge of parasitic extraction, signal integrity, timing impact, and layout optimization techniques.
- Experience collaborating within cross-functional semiconductor design teams.
Preferred Experience- Hands-on experience with FinFET and sub-7nm technology nodes.
- Experience with high-speed digital, mixed-signal, or advanced SoC designs.
- Familiarity with layout automation and scripting using SKILL, Python, TCL, or similar languages.
- Track record supporting successful production tapeouts.
We offer a competitive hourly rate ranging from $65 to $80 per hour, based on experience, skills, and qualifications. The position includes a comprehensive benefits package and bonus opportunities
Full-Time Benefits:• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
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