Job Description:We are seeking a Senior Engineer I - design to join our team. This role involves RTL design, functional verification, and contributing to next-generation mixed-signal and digital products. The ideal candidate combines strong hardware design fundamentals with modern AI/ML-assisted design methodologies and software skills to improve design productivity and verification quality.
Responsibilities
- Design, code, and optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC implementation
- Develop and execute verification plans using UVM/SystemVerilog-based testbenches
- Write constrained-random and directed tests to achieve functional and code coverage targets
- Apply AI/ML techniques to improve verification closure, coverage analysis, regression optimization, and bug triaging
- Develop scripts and automation tools (Python, TCL) to streamline design and verification workflows
- Collaborate with architecture, analog, physical design, and software teams to ensure design correctness and integration
- Perform lint, CDC, and synthesis checks; resolve issues through the design cycle
- Participate in design reviews, specification development, and documentation
Requirements/Qualifications:- BSEE with course emphasis on microelectronics and 5 years of experience required.
- Proficiency in Verilog and/or SystemVerilog for RTL design
- Experience with UVM-based verification environments
- Understanding of digital design fundamentals: timing, synthesis constraints, clock domain crossings
- Programming skills in Python; familiarity with TCL or shell scripting
- Experience with industry EDA tools (Synopsys, Cadence, or Siemens) will be plus.
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Preferred Qualifications:
- Masters in Electrical Engineering
Travel Time:0% - 25%
Physical Attributes:Hearing, Seeing, Talking, Works Around Others
Physical Requirements:80% Sitting, 10% Standing, 10% Walking
