Job Details:Job Description: The Role and Impact
Join Intel's CPU Design Team and help shape the future of energy-efficient, high-performance computing. As a Senior CPU RTL Design Engineer, you will define, develop, and optimize key microarchitectural features that power Intel's next-generation processors.
In this role, you will contribute to CPU architecture and microarchitecture development, create high-quality RTL designs, and drive power, performance, area, and timing optimizations. Working closely with architecture, verification, physical design, and SoC integration teams, you will help deliver innovative processor technologies that advance Intel's leadership in computing.
This position offers the opportunity to solve complex technical challenges, influence CPU design decisions, and contribute to products that impact millions of users worldwide.
What You’ll Do
Key responsibilities will include but not limited to:
- Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU.
- Participate in defining the architecture and microarchitecture features of the CPU design.
- Write RTL and optimize logic for power, performance, area, and timing goals.
- Ensure design integrity for physical implementation through effective strategies, tools, and methods.
- Review verification plans to ensure design features are correctly validated and resolve failing RTL tests.
- Document microarchitectural specifications (MAS) for the CPU features.
- Collaborate with SoC customers to ensure seamless integration and high-quality performance of the CPU block
Behavioral Traits that we are looking for:
Strong Ownership: Takes responsibility for complex technical deliverables and drives issues to closure.
Technical Curiosity: Continuously seeks deeper understanding of architecture, design tradeoffs, and emerging technologies.
Bias for Action: Identifies issues early and proactively develops solutions.
Collaboration: Works effectively across architecture, verification, physical design, SOC integration, methodology, and validation teams.
Communication: Clearly communicates technical concepts, design decisions, and tradeoffs, while fostering effective collaboration across cross-functional engineering teams.
Critical Thinking: Uses data and engineering rigor to evaluate alternatives and make decisions.
Continuous Improvement: Looks for opportunities to improve design quality, efficiency, methodologies, and development processes.
Influence Without Authority: Builds alignment and drives technical decisions through expertise and collaboration.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note:
Minimum Qualifications and Experience:
Bachelor's degree in Electrical/Computer Engineering, Computer science or related STEM degree with 7+ years of relevant experience. Or a Master's degree in the same filed with 5+ years of experience.
In addition, you must have the following experience:
- 7+ years of experience in RTL design using System Verilog, with strong knowledge of hardware modeling and logic debug environments.
- 5+ years of experience with energy-efficient and low-power logic design methods, including techniques applicable to high-frequency optimization.
- 5+ years of experience in Clock-domain crossing (CDC), and Power-aware design.
- 3+ years of experience in scripting languages such as TCL, Perl, or Python.
Preferred Qualifications and Experience:
- A PhD in the same fields with 2+ years of experience.
- Knowledge on CPU power-management namely power/electrical budgeting, dynamic voltage and frequency scaling, thermal, P/C states and reset sequence handling.
- Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
- Experience with high-speed circuit design and optimization, specifically for datapath, circuits, and arrays.
- Familiarity with circuit planning and timing convergence processes.
- Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
- Proficient with static timing analysis, UPF and lint checks.
Join Intel and be part of a team that is passionate about shaping the future of technology. Apply today and embark on a career journey that makes a difference.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location: US, Texas, Austin
Additional Locations:US, Arizona, Phoenix
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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