About the roleAs a Senior Software Engineer on the Boulder Opal team, you will lead the design and evolution of the compiler that powers next-generation quantum computing systems. Working closely with researchers and quantum engineers, you will bridge the gap between quantum algorithms and physical hardware by building a high-performance compiler capable of translating pulse-level programs into controller instructions.
This is a hands-on senior engineering role for someone with deep compiler expertise who enjoys solving challenging systems problems and influencing technical direction.
What you'll be doing:- Design, implement and optimise compiler infrastructure, intermediate representations, optimisation passes and code generation.
- Maintain and evolve our bespoke Python DSL used by researchers to construct pulse-level quantum programs.
- Build high-performance software using Python and C++.
- Work closely with researchers to translate experimental algorithms into production-quality compiler capabilities.
- Run experiments on quantum hardware to validate compiler outputs end-to-end.
- Influence technical direction, mentor other engineers and drive engineering best practices.
Ideally you'll have:- Strong proficiency in Python and C++.
- Experience with LLVM, particularly MLIR.
- Experience implementing language tooling, parsers or DSLs.
- Significant experience designing production compiler systems.
- Experience with compiler architectures, intermediate representations, optimisation passes and code generation.
- Strong understanding of systems programming and software architecture.
It would be fantastic (but not essential) if you bring:- Experience with quantum control systems or pulse-level programming.
- Experience with experimental characterisation of superconducting or semiconductor spin qubits.
- Experience with RF signal processing concepts such as IQ modulation.
- Experience using laboratory instrumentation (AWGs, digitisers, oscilloscopes, SCPI-controlled instruments).
- Experience with FPGA development (Verilog, VHDL or HLS).
SalaryThe base salary for this position is targeted between $135,000 - $210,000 and will ultimately be determined by specific job-related skills, experience, level, location and other contributing factors. Depending on the position offered, this role may be eligible for annual discretionary bonuses, equity and other forms of compensation outside of the targeted range. For more information on benefits at Q-CTRL, please visit our careers page at https://q-ctrl.com/careers.
Should you have any questions related to the compensation package, please speak directly with the Talent Acquisition representative.
