Senior Circuit Design Engineer - AI & HPC (7708)

Taiwan Semiconductor Manufacturing Company Limited

$120K — $165K *
Consumer Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Master's degree plus 3+ years of experience, or Ph.D. in VLSI design or custom circuits.
  • Expertise in VLSI design, digital integrated circuits, Verilog, logic design, and DFT.
  • Hands-on experience with SPICE simulations for custom circuits.
  • Strong teamwork and communication skills, with a collaborative mindset.

Responsibilities

  • Design custom memory circuits for AI and HPC applications.
  • Lead PPA optimization for SRAM circuits in line with scaling advancements.
  • Conduct detailed technical analysis for performance improvements.
  • Guide layout, manage design characterization, and oversee methodologies.
  • Collaborate with RTL and PD teams for optimal IP PPA integration.
  • Code compilers and interpret testing results.

Benefits

  • Market competitive pay and bonuses.
  • Comprehensive benefits package.
  • Opportunities for professional development.
  • Flexible hybrid work schedule, with 4 days in-office.
Full Job Description
Step into a pivotal role within our San Jose design R&D team and position yourself at the forefront of the global semiconductor industry. As a Senior Circuit Design Engineer, you will leverage TSMC's leading process technology and design enablement solutions to push the boundaries of semiconductor manufacturing. In this role, you will focus on AI and high-performance computing applications, unleashing innovation and driving next-generation advancements. You will join us in our San Jose office, operating on a hybrid work schedule with 4 days in-office. Responsibilities • Design custom memory circuits and architectures tailored specifically for AI and HPC applications. • Lead efforts in Power, Performance, and Area (PPA) optimization for custom SRAM circuits to align with advanced scaling advancements. • Perform comprehensive technical analysis, including Time/Power/Area improvements, Read/Write margin, Noise, and Power/Signal IR/EM analysis. • Provide supervised layout guidance, manage design characterization, and oversee methodology, verification, and final sign-off. • Collaborate closely with RTL and Physical Design (PD) teams to ensure the best IP PPA integration. • Handle compiler coding and the interpretation of testing results. Minimum Qualifications • Master's degree with 3+ years of relevant industry experience, or a Ph.D. demonstrating applicable academic research in VLSI design or custom circuits. • In-depth knowledge of VLSI design, digital integrated circuits, Verilog, logic design, and DFT. • Hands-on experience running SPICE simulations for custom circuits. • A collaborative mindset with a strong teamwork attitude and excellent communication skills. Preferred Qualifications • Advanced knowledge of leading-edge process nodes (TSMC N7 and below), ideally with a track record of successfully delivering product tapeouts below 5nm. • Deep expertise in high-speed and low-power custom SRAM or Register File architecture and implementation. • Prior experience acting as a technical lead for customer IP products or energy-efficient AI inference/training accelerators is a significant asset. • Proficiency with memory characterization and industry-standard EDA tools. • Familiarity with scripting and automation (Perl, TCL, Python) is highly advantageous and will allow you to hit the ground running. Pay Transparency / Benefits statement At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $120,000 and $165,000 per year. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC's total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs. Date: May 30, 2026 Country/Region: US City: San Jose Company: TSMC Technology, Inc.

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