Description

Do you love building and prototyping robust electrical systems?

Are you passionate about providing real impact to the country's toughest national security problems?

If so, we're looking for someone like you to join our team at APL.

The Miniature Device Technologies Group develops highly customized tools and techniques required to carry out missions around the globe. Whether it be a quick reaction need from the field or the long-term development of a novel capability, we work hand in hand with our government sponsors to conceive and realize solutions to their most challenging problems. We leverage our multi-disciplinary set of capabilities in custom application-specific integrated circuits (ASIC), printed circuit board (PCB), embedded software, field-programmable gate array (FPGA), and signal processing design to create ultra-small, low-power solutions that exceed comparable commercial alternatives.

We are seeking an experienced senior physical design ASIC design engineer, to help us advance the state-of-the-art in miniature systems for a wide range of applications. In this role, you will be responsible for all back-end flow aspects, including synthesis, top-level floor-planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks. You will be working closely with the ASIC design team to identify back-end issues, and assist in addressing these issues, both in the RTL and gate-level phases of the design. You will help explore process selection for new proposals and designs, assessing aspects such as achievable size and power, and availability of the necessary design features and intellectual property (IP.) Additionally, you will perform custom physical design as needed, both to complete custom block layouts, and to perform custom modifications necessary at the top level of the ASIC.

As a Senior ASIC Physical Design Engineer...

• Your primary responsibility will be digital back-end flow, from synthesis to a completed, verified top-level layout, ready for tapeout submission
• You will contribute to process selection for new designs and proposals
• You will floorplan the top-level layout of the digital and mixed-signal ASICs
• You will perform timing analysis and design partitioning
• You will perform SCAN and BIST insertion for maximum defect coverage
• You will work with digital designers to debug and address back-end related RTL and gate-level issues
• You will perform all physical verification, including DRC, DRC+, MCD, and LVS
• You will perform custom physical layout
• You may assist with ASIC design environment enhancements and scripting
• You will demonstrate initiative by identifying and driving process improvements, and implementing innovative solutions to complex design challenges
• You will build and maintain strong working relationships with cross-functional teams, including digital design, verification, and software teams
• You will provide leadership and guidance to junior physical design engineers, and contribute to their growth and development
• You will collaborate with the team to achieve project goals and objectives, and drive results through effective teamwork and problem-solving
• You will foster open communication and collaboration with digital designers, junior physical design engineers, and other stakeholders to ensure seamless project execution

Qualifications

You meet our minimum qualifications for the job if you...

• Possess an Associate's degree in a technical field, or a combination of equivalent level experience/education/certifications.
• Are skilled at using Cadence ASIC design tools for back-end flow implementation
• Are skilled at using Siemens Calibre physical verification tools
• Have 6+ years of experience specifically performing back-end ASIC design
• Are able to obtain an Interim Secret level security clearance by your start date and can ultimately obtain a Secret level clearance. If selected, you will be subject to a government security clearance investigation and must meet the requirements for access to classified information. Eligibility requirements include U.S. citizenship.

You'll go above and beyond our minimum requirements if you...

• Have experience with custom physical layout in Cadence Virtuoso
• Are skilled at using Siemens ASIC design tools for back-end flow implementation
• Have extensive knowledge and experience in ASIC technology characterization for process selection
• Hold an active clearance and/or have successfully undergone single-scope background investigations in the past.

Minimum Rate

$105,000 Annually

Maximum Rate

$290,000 Annually