Advanced Micro Devices, Inc

RTL Design Engineer

Advanced Micro Devices, Inc$100K — $130K *
Enterprise Technology
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • 5-7 years of RTL design experience in digital IP/subsystems
  • Proven ownership from architecture through tape-out
  • Strong accuracy and attention to detail
  • Excellent communication and problem-solving skills
  • Familiarity with PCIe protocol and subsystem design is a plus
  • Proficient in Verilog/SystemVerilog, VCS simulation, and scripting languages
  • Bachelor's or Master's degree in Electrical or Computer Engineering

Responsibilities

  • Design micro-architecture and RTL for PCIe subsystem blocks
  • Develop and maintain RTL for complex digital blocks
  • Translate architecture requirements into high-quality RTL
  • Drive design reviews and resolve RTL issues
  • Support subsystem integration and SoC delivery
  • Ensure RTL complies with signoff criteria like Lint and STA
  • Collaborate with cross-functional teams for design handoff

Benefits

  • Comprehensive AMD benefits package
  • Hybrid work arrangement available
  • Opportunities for mentoring and professional development
  • Collaborative culture with cross-functional teams
  • Focus on innovation in a critical technology space
Full Job Description
Responsibilities

THE ROLE:

As a member of AMD's PCIe Subsystem (PCIeSS) organization, you will join the PCIe IP Enablement (IPE) team as a senior RTL design engineer. You will work closely with the architecture, IP design, physical design, verification, and DFx teams to design and deliver high-quality PCIe subsystem RTL and achieve first-pass silicon success.

THE PERSON:

A successful candidate with RTL design experience, with provenend-to-end ownership of complex digital IP/subsystems from architecture through tape-out. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills, and will help set design development direction and mentor other engineers on the team.

KEY RESPONSIBILITIES:

  • Micro-architecture and RTL design for PCIe subsystem blocks
  • Develop and maintain RTL for complex digital blocks; author and enforce RTL coding guidelines and design documentation
  • Translate architecture requirements into robust, reusable, high-quality RTL
  • Drive design reviews and resolve complex RTL debug and correctness issues
  • Support subsystem integration and SoC delivery
  • Ensure RTL closes cleanly through front-end signoff 6 Lint, CDC/RDC, synthesis, LEC, STA
  • Collaborate with verification, physical design, and architecture teams for seamless design handoff and sign-off

PREFERRED EXPERIENCE:

  • Strong RTL design and micro-architecture experience on complex digital IP/subsystems, from RTL to tape-out
  • Strong AI knowledge and experience in it's usage to develop skills and agents.
  • Direct PCIe protocol and subsystem design experience 6 a strong plus
  • Proficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA
  • Experience with Verilog / SystemVerilog RTL design, VCS simulation, and Perl/Shell scripting
  • Familiarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD)
  • Excellent problem-solving and debugging skills

ACADEMIC CREDENTIALS:

  • Bachelor's or Master's degree in Electrical Engineering / Computer Engineering

LOCATION: Markham & Vancouver

 

 

 

 

 

 

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Qualifications

Benefits offered are described:  AMD benefits at a glance.

 

This posting is for an existing vacancy.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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