Product Engineer (Yield & Quality)

Taiwan Semiconductor Manufacturing Company Limited

$90K — $130K *
Manufacturing & Automotive
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Master's Degree in Electrical Engineering required
  • Experience in semiconductor physics and CMOS device operation preferred
  • Familiarity with digital circuit design preferred
  • Strong problem-solving skills
  • Excellent communication and collaboration abilities
  • Capability to work under pressure and with mission orientation
  • Willingness to travel and train for 6-9 months in Taiwan

Responsibilities

  • Lead team to identify root causes for chip performance and quality issues
  • Analyze test data logs to pinpoint failure modes
  • Conduct electrical and physical failure analyses
  • Collaborate with integration and process teams to develop corrective actions
  • Verify effectiveness of implemented actions
  • Support early-stage product design for successful tape-outs
  • Perform design rule assessments and layout reviews for product robustness

Benefits

  • Work in a dynamic and innovative environment
  • Opportunities for professional growth and development
  • Collaboration with leading experts in semiconductor technology
  • Engagement in impactful projects influencing global markets
  • Potential for international experience and training in Taiwan
Full Job Description
Product Design Engineer, Yield & Quality

TSMC Arizona is looking for Product Design Engineers to join our 5-nanometer fab, located in sunny Phoenix, Arizona. As a Product Engineer, you will demonstrate a strong sense of reliability and enthusiasm and will possess an attitude that embodies our core values - Integrity, Commitment, Innovation and Customer Trust.

TSMC Arizona's Product Designer is responsible for early-stage design, yield window performance, and identify root cause for chip performance.

Job Description:
  • Lead team to identify root cause for N5/N4 chip performance / yield / quality issues:
  • Analyze CP test bin / data log to identify failure mode
  • Electrical failure analysis and physical failure analysis to locate suspect process stage
  • Work with Fab integration team or process team to define corrective actions / solutions
  • Trace action implementation to verify effectiveness
  • Product early-stage design support to help product tape-out smoothly and Si success:
  • Design rule review & assessment for robust product design
  • Layout review or DFM to enlarge manufacturing window
  • Yield window characterization and device sweet spot identification for the best yield / performance process condition.


Minimum Qualifications:
  • Applicants must be legally eligible to work in the United States and have:
  • The ability to travel and train in Taiwan for 6 - 9 months
  • Master's Degree in Electrical Engineering, required
  • Working knowledge of semiconductor physics, CMOS device operation, and advanced semiconductor manufacturing is preferred
  • Familiar with digital circuit design is preferred.
  • Able to work within cross-functional teams.
  • Consistent problem-solving skills, communication abilities, and active learning
  • Able to work under pressure and mission orientation


Work Location: Phoenix, AZ

Training Location: Phoenix

Travel Percentage: As Required

Date: Jul 2, 2026

Country/Region: US

City: Phoenix

Company: TSMC Arizona

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