Job Details:Job Description:The Role and ImpactAs a Product Development Engineer - Scan Diagnostics, you will play a core role in shaping Intel's product innovation and manufacturing excellence. Your efforts will be pivotal in transforming cutting-edge integrated circuits from design feasibility to high-volume production. This role offers exceptional learning and growth opportunities, providing broad exposure to the entire semiconductor product lifecycle, from initial definition to HVM. By collaborating with cross-functional teams, you will influence product design, ensure seamless production ramp-up, and directly contribute to delivering world-class solutions to Intel's customers. You'll engage in advanced diagnostic techniques for fault identification and yield improvement, collaborating with stakeholders across the company and our supplier ecosystem.
Key Responsibilities- Create, Enable and Support Scan/Chain Diagnosis infrastructure and processes for Intel's HVM products.
- Support fail-based and volume diagnostic analysis and yield analysis requests to drive continuous yield improvement.
- Support CAD infrastructure and computational resources for Diagnostics across all HVM product lines.
- Develop and optimize tools, methods, and flows for Design for Test (DFT), diagnostics, and yield analysis.
- Collaborate with external vendors and internal teams to establish standard industry practices for diagnostics and yield analysis.
- Maintain relationships with Electronic Design Automation (EDA) vendors to access the latest tools and methodologies.
- Facilitate knowledge transfer to ensure Yield Management and Failure Analysis team members are updated with the latest methodologies and tools.
- Define and monitor DFX quality metrics (coverage, test cost, and debuggability) from development to production ramp-up.
- Work closely with Design and New Product Introduction (NPI) teams to ensure diagnostic readiness for new products.
Qualifications:Minimum Qualifications:- Candidate must possess at least a bachelor's degree in engineering or related field. Master's degree or Ph.D. preferred.
- 4+ years of experience in DFT, Scan Diagnostics enablement, Post-Si diagnostics debug, Yield Analysis, and/or EDA tools.
- Proficiency in at least one of the following: Python, TCL, C-Shell, or PERL scripting.
- Seeking candidates with strong communication and teamwork skills.
Preferred Qualifications: - Experience with Siemens's Tessent Test and Yield Analysis tools or similar.
- Experience with Synopsys's Yield Explorer or similar tools.
- Experience with SOC / IP DFT control architecture (e.g., JTAG, IJTAG, IEEE1500).
- Experience in Custom and/or ASIC circuit design.
We are looking for innovators and problem-solvers to join our team and help us continue to redefine the future of technology. If you are passionate about making an impact and growing your career in a dynamic and collaborative environment, apply now.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, California, Santa Clara
Additional Locations:US, Arizona, Phoenix, US, Oregon, Hillsboro
Business group:The Corporate Planning Group (CPG) is the strategic heartbeat of Intel, acting as catalyst for innovation and transformation, guiding the company towards achieving its vision and maintaining a competitive edge in the marketplace. CPG exists to build a comprehensive operating plan that leverages internal and external manufacturing for Intel's growth. We emphasize data-driven innovation and results, ensuring we meet customer demands and financial targets. Join CPG to be part of a forward-looking group that is not just planning for tomorrow, but redefining it.
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
