GlobalFoundries

Principal SoC Design Engineer

GlobalFoundries$153K — $265K *
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
  • 8-10+ years of hands-on experience in SoC/IP design for safety-critical applications.
  • Expert-level proficiency in SystemVerilog/Verilog and advanced digital design techniques.
  • Strong command of SoC interconnects and protocols including AXI4/5 and NoC fabrics.
  • Proven track record leading RTL development on advanced nodes (7nm and below).
  • Proficiency in scripting languages like Python for RTL generation and automation.
  • Exceptional analytical and problem-solving skills for cross-domain challenges.

Responsibilities

  • Lead the analysis and translation of SoC-level requirements into micro-architecture specifications.
  • Architect and develop synthesizable RTL for high-performance IP modules and full SoC integrations.
  • Drive improvements in front-end design flow and automation strategies to enhance productivity.
  • Perform detailed RTL design reviews and optimizations to ensure silicon success.
  • Integrate emerging standards and processor architectures into production flows.
  • Collaborate with cross-functional teams to resolve design issues and define interfaces.
  • Provide technical guidance through reviews and knowledge sharing on RTL best practices.

Benefits

  • Collaborative work environment with multidisciplinary teams.
  • Opportunities for professional growth and development.
  • Involvement in cutting-edge projects in data processing and automotive microcontrollers.
Full Job Description
Principal Engineer SoC Design

Introduction:
The Principal SoC Design Engineer provides deep technical expertise in developing high-performance data processing units and automotive microcontrollers with 8-10+ years of experience. This individual contributor role drives end-to-end SoC design-from architecture definition and micro-architecture specification to RTL implementation, optimization, and silicon-proven delivery-while advancing design methodologies for complex, safety-critical systems.

Your Job:
  • Lead gathering, analysis, and translation of complex subsystem, module, and SoC-level requirements into actionable micro-architecture specifications that meet stringent performance, power, and area targets.
  • Architect and develop synthesizable RTL (SystemVerilog/Verilog) for high-performance IP modules, subsystems, and full SoC integrations, including custom data processing units and automotive MCU cores.
  • Drive front-end design flow improvements, including automation of spec-to-RTL generation, IP reuse strategies, and advanced synthesis methodologies to boost team productivity and design quality.
  • Perform detailed RTL design reviews, optimization for timing/power/area, and constraint development to ensure first-pass silicon success across advanced nodes.
  • Champion design innovation by evaluating and integrating emerging standards, bus fabrics (AXI5/CHI, AMBA), and processor architectures (RISC-V, ARM Cortex) into production flows.
  • Collaborate deeply with architecture, verification, physical design, DFT, and software teams to resolve multi-disciplinary issues, define interfaces, and align on system-level tradeoffs.
  • Provide technical guidance through code reviews and knowledge sharing on best practices for maintainable, verifiable RTL.
  • Analyze silicon bring-up results, debug field issues, and implement lessons learned to refine design methodologies and IP libraries.

Other Responsibilities:
  • Collaborate with cross-functional teams (Architecture, Verification, Physical Design, etc.) to identify and resolve design issues.

Required Qualifications:
  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
  • 8-10+ years of hands-on experience in SoC/IP design for high-volume or safety-critical applications, including architecture-to-silicon delivery.
  • Expert-level proficiency in synthesizable SystemVerilog/Verilog, with deep knowledge of advanced digital design techniques (pipelining, FSM optimization, low-power design).
  • Strong command of SoC interconnects and protocols including AXI4/5, AHB, APB, CHI, and NoC fabrics.
  • Proven track record of leading RTL development for complex blocks (processors, accelerators, peripherals) on advanced nodes (7nm and below).
  • Proficiency in scripting (Python, Tcl, Perl) for RTL generation, automation, and design space exploration.
  • Exceptional analytical, problem-solving, and debugging skills for resolving ambiguous, cross-domain challenges.
  • Outstanding technical communication skills for presenting designs to stakeholders and documenting specifications.


Preferred Qualifications:
  • Experience with RISC-V, ARM Cortex-A/R/M-series, or MIPS architectures in automotive or embedded applications.
  • Deep expertise in Functional Safety (ISO 26262 ASIL-D), including safety mechanisms, fault injection, and certification flows.
  • Familiarity with register description languages (IP-XACT, SystemRDL) and UVM-based verification methodologies.
  • Hands-on experience with high-performance data processing units (e.g., DSPs, AI accelerators, vision pipelines).
  • Proven technical leadership in driving design methodology evolution and tool adoption (Synopsys DC, Genus, Verdi).


Expected Salary Range
$153,000.00 - $265,000.00

The exact Salary will be determined based on qualifications, experience and location.

If you need a reasonable accommodation for any part of the employment process, please contact us by email at [email protected] and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.

An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.

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