Responsibilities- Provide technical leadership throughout all phases of ASIC and SoC development, with primary focus on early architecture definition and specification of Network-on-Chip (NoC), memory/interconnect subsystems for high-performance AI and compute SoCs.
- Define system-level address maps, memory hierarchy, and SoC connectivity. Translate product performance objectives into scalable NoC, memory, and data movement architectures.
- Drive technical evaluations and provide recommendations for third-party IP, silicon technologies, and vendor solutions, balancing performance, power, area, schedule, and risk considerations.
- Partner with performance modeling and analysis teams to define performance requirements, develop architectural models, and identify system bottlenecks early in the design cycle.
- Collaborate closely with hardware, firmware, software, and system architecture teams to ensure architectural alignment and successful feature integration.
- Guide design and verification teams throughout development, ensuring implementation fidelity to architectural intent and requirements.
- Support pre-silicon validation, post-silicon bring-up, and performance characterization activities to ensure delivered features meet functional and performance goals.
- Drive cross-functional technical reviews, resolve complex architectural issues, and provide leadership on critical design tradeoffs and system-level decisions.
QualificationsRequired qualifications
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
- OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
- OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
- OR equivalent experience.
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred qualifications
10+ years of architecture and design experience in large scale SoC
Understanding of on-chip interconnect and memory hierarchy
Experience with SoC architecture
Track record of successful design of IPs and SoCs.
Experience in caches and cache coherency
Experience with SOC used in data center
Experience with Security, die-to-die interconnect, debug, telemetry, boot/reset, RAS
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
