Principal PLL Design Engineer

Celero Communications, Inc.

• $110K — $130K *
Telecommunications & Hardware
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Master's degree or PhD in Electrical Engineering or related fields
  • 5+ years of experience in PLL design and production-level tape-out
  • Expertise in advanced node technologies (16nm to 2nm processes)
  • Profound knowledge of phase noise analysis and VCO design
  • Proficient in Cadence Virtuoso and system-level modeling software like MATLAB

Responsibilities

  • Understand and evaluate PLL topology trade-offs for specific performance metrics
  • Architect, design, and simulate PLL building blocks at the transistor level
  • Address challenges in advanced technology nodes, including noise optimization
  • Supervise layout engineers to ensure optimal design implementation
  • Conduct PLL bring-up in lab and performance characterization
  • Perform system-level simulations for PLL compatibility with transceiver technologies

Benefits

  • Opportunity to work with cutting-edge optical and high-speed SerDes technologies
  • Collaborative environment within a fast-growing start-up
  • Influential role in shaping the future of next-gen AI technology
  • Access to advanced lab equipment for practical experimentation
  • A chance to lead design initiatives with significant industry impact
Full Job Description
Principal PLL Design Engineer

About the job
Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer -who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.

What You Will Do
• Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range
• Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization
• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies
• Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
• Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies

What You Will Bring
• Master's degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience.
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs
• Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling
• Strong communication and documentation skills

Javier Leon
Talent Acquisition

[email protected]
www.celero.inc

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